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Move QOM typedefs and add missing includes 

Some typedefs and macros are defined after the type check macros.
This makes it difficult to automatically replace their
definitions with OBJECT_DECLARE_TYPE.

Patch generated using:

 $ ./scripts/codeconverter/converter.py -i \
   --pattern=QOMStructTypedefSplit $(git grep -l '' -- '*.[ch]')

which will split "typdef struct { ... } TypedefName"
declarations.

Followed by:

 $ ./scripts/codeconverter/converter.py -i --pattern=MoveSymbols \
    $(git grep -l '' -- '*.[ch]')

which will:
- move the typedefs and #defines above the type check macros
- add missing #include "qom/object.h" lines if necessary

Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Message-Id: <20200831210740.126168-9-ehabkost@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Message-Id: <20200831210740.126168-10-ehabkost@redhat.com>
Message-Id: <20200831210740.126168-11-ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
This commit is contained in:
Eduardo Habkost 2020-09-03 16:43:22 -04:00
parent 1c8eef0227
commit db1015e92e
796 changed files with 3378 additions and 1823 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
accel/tcg/tcg-all.c
View File

@ -36,12 +36,13 @@
#include "hw/boards.h"
#include "qapi/qapi-builtin-visit.h"
typedef struct TCGState {
struct TCGState {
AccelState parent_obj;
bool mttcg_enabled;
unsigned long tb_size;
} TCGState;
};
typedef struct TCGState TCGState;
#define TYPE_TCG_ACCEL ACCEL_CLASS_NAME("tcg")

5
backends/cryptodev-builtin.c
View File

@ -26,6 +26,7 @@
#include "qapi/error.h"
#include "standard-headers/linux/virtio_crypto.h"
#include "crypto/cipher.h"
#include "qom/object.h"
/**
@ -34,12 +35,12 @@
*/
#define TYPE_CRYPTODEV_BACKEND_BUILTIN "cryptodev-backend-builtin"
typedef struct CryptoDevBackendBuiltin
CryptoDevBackendBuiltin;
#define CRYPTODEV_BACKEND_BUILTIN(obj) \
OBJECT_CHECK(CryptoDevBackendBuiltin, \
(obj), TYPE_CRYPTODEV_BACKEND_BUILTIN)
typedef struct CryptoDevBackendBuiltin
CryptoDevBackendBuiltin;
typedef struct CryptoDevBackendBuiltinSession {
QCryptoCipher *cipher;

6
backends/cryptodev-vhost-user.c
View File

@ -30,6 +30,7 @@
#include "sysemu/cryptodev-vhost.h"
#include "chardev/char-fe.h"
#include "sysemu/cryptodev-vhost-user.h"
#include "qom/object.h"
/**
@ -38,12 +39,13 @@
*/
#define TYPE_CRYPTODEV_BACKEND_VHOST_USER "cryptodev-vhost-user"
typedef struct CryptoDevBackendVhostUser CryptoDevBackendVhostUser;
#define CRYPTODEV_BACKEND_VHOST_USER(obj) \
OBJECT_CHECK(CryptoDevBackendVhostUser, \
(obj), TYPE_CRYPTODEV_BACKEND_VHOST_USER)
typedef struct CryptoDevBackendVhostUser {
struct CryptoDevBackendVhostUser {
CryptoDevBackend parent_obj;
VhostUserState vhost_user;
@ -51,7 +53,7 @@ typedef struct CryptoDevBackendVhostUser {
char *chr_name;
bool opened;
CryptoDevBackendVhost *vhost_crypto[MAX_CRYPTO_QUEUE_NUM];
} CryptoDevBackendVhostUser;
};
static int
cryptodev_vhost_user_running(

1
backends/dbus-vmstate.c
View File

@ -19,6 +19,7 @@
#include "qapi/qmp/qerror.h"
#include "migration/vmstate.h"
#include "trace.h"
#include "qom/object.h"
typedef struct DBusVMState DBusVMState;
typedef struct DBusVMStateClass DBusVMStateClass;

3
backends/hostmem-file.c
View File

@ -17,11 +17,12 @@
#include "sysemu/hostmem.h"
#include "sysemu/sysemu.h"
#include "qom/object_interfaces.h"
#include "qom/object.h"
typedef struct HostMemoryBackendFile HostMemoryBackendFile;
#define MEMORY_BACKEND_FILE(obj) \
OBJECT_CHECK(HostMemoryBackendFile, (obj), TYPE_MEMORY_BACKEND_FILE)
typedef struct HostMemoryBackendFile HostMemoryBackendFile;
struct HostMemoryBackendFile {
HostMemoryBackend parent_obj;

3
backends/hostmem-memfd.c
View File

@ -17,13 +17,14 @@
#include "qemu/memfd.h"
#include "qemu/module.h"
#include "qapi/error.h"
#include "qom/object.h"
#define TYPE_MEMORY_BACKEND_MEMFD "memory-backend-memfd"
typedef struct HostMemoryBackendMemfd HostMemoryBackendMemfd;
#define MEMORY_BACKEND_MEMFD(obj) \
OBJECT_CHECK(HostMemoryBackendMemfd, (obj), TYPE_MEMORY_BACKEND_MEMFD)
typedef struct HostMemoryBackendMemfd HostMemoryBackendMemfd;
struct HostMemoryBackendMemfd {
HostMemoryBackend parent_obj;

6
backends/rng-builtin.c
View File

@ -9,13 +9,15 @@
#include "sysemu/rng.h"
#include "qemu/main-loop.h"
#include "qemu/guest-random.h"
#include "qom/object.h"
typedef struct RngBuiltin RngBuiltin;
#define RNG_BUILTIN(obj) OBJECT_CHECK(RngBuiltin, (obj), TYPE_RNG_BUILTIN)
typedef struct RngBuiltin {
struct RngBuiltin {
RngBackend parent;
QEMUBH *bh;
} RngBuiltin;
};
static void rng_builtin_receive_entropy_bh(void *opaque)
{

7
backends/rng-egd.c
View File

@ -16,17 +16,18 @@
#include "qapi/error.h"
#include "qapi/qmp/qerror.h"
#include "qemu/module.h"
#include "qom/object.h"
#define TYPE_RNG_EGD "rng-egd"
typedef struct RngEgd RngEgd;
#define RNG_EGD(obj) OBJECT_CHECK(RngEgd, (obj), TYPE_RNG_EGD)
typedef struct RngEgd
{
struct RngEgd {
RngBackend parent;
CharBackend chr;
char *chr_name;
} RngEgd;
};
static void rng_egd_request_entropy(RngBackend *b, RngRequest *req)
{

6
backends/tpm/tpm_emulator.c
View File

@ -42,8 +42,10 @@
#include "qapi/qapi-visit-tpm.h"
#include "chardev/char-fe.h"
#include "trace.h"
#include "qom/object.h"
#define TYPE_TPM_EMULATOR "tpm-emulator"
typedef struct TPMEmulator TPMEmulator;
#define TPM_EMULATOR(obj) \
OBJECT_CHECK(TPMEmulator, (obj), TYPE_TPM_EMULATOR)
@ -63,7 +65,7 @@ typedef struct TPMBlobBuffers {
TPMSizedBuffer savestate;
} TPMBlobBuffers;
typedef struct TPMEmulator {
struct TPMEmulator {
TPMBackend parent;
TPMEmulatorOptions *options;
@ -80,7 +82,7 @@ typedef struct TPMEmulator {
unsigned int established_flag_cached:1;
TPMBlobBuffers state_blobs;
} TPMEmulator;
};
struct tpm_error {
uint32_t tpm_result;

3
backends/tpm/tpm_passthrough.c
View File

@ -33,8 +33,10 @@
#include "qapi/clone-visitor.h"
#include "qapi/qapi-visit-tpm.h"
#include "trace.h"
#include "qom/object.h"
#define TYPE_TPM_PASSTHROUGH "tpm-passthrough"
typedef struct TPMPassthruState TPMPassthruState;
#define TPM_PASSTHROUGH(obj) \
OBJECT_CHECK(TPMPassthruState, (obj), TYPE_TPM_PASSTHROUGH)
@ -53,7 +55,6 @@ struct TPMPassthruState {
size_t tpm_buffersize;
};
typedef struct TPMPassthruState TPMPassthruState;
#define TPM_PASSTHROUGH_DEFAULT_DEVICE "/dev/tpm0"

6
chardev/baum.c
View File

@ -33,6 +33,7 @@
#include <brlapi.h>
#include <brlapi_constants.h>
#include <brlapi_keycodes.h>
#include "qom/object.h"
#if 0
#define DPRINTF(fmt, ...) \
@ -86,7 +87,7 @@
#define BUF_SIZE 256
typedef struct {
struct BaumChardev {
Chardev parent;
brlapi_handle_t *brlapi;
@ -100,7 +101,8 @@ typedef struct {
uint8_t out_buf_used, out_buf_ptr;
QEMUTimer *cellCount_timer;
} BaumChardev;
};
typedef struct BaumChardev BaumChardev;
#define TYPE_CHARDEV_BRAILLE "chardev-braille"
#define BAUM_CHARDEV(obj) OBJECT_CHECK(BaumChardev, (obj), TYPE_CHARDEV_BRAILLE)

6
chardev/char-pty.c
View File

@ -33,15 +33,17 @@
#include "qemu/qemu-print.h"
#include "chardev/char-io.h"
#include "qom/object.h"
typedef struct {
struct PtyChardev {
Chardev parent;
QIOChannel *ioc;
int read_bytes;
int connected;
GSource *timer_src;
} PtyChardev;
};
typedef struct PtyChardev PtyChardev;
#define PTY_CHARDEV(obj) OBJECT_CHECK(PtyChardev, (obj), TYPE_CHARDEV_PTY)

6
chardev/char-ringbuf.c
View File

@ -29,16 +29,18 @@
#include "qemu/base64.h"
#include "qemu/module.h"
#include "qemu/option.h"
#include "qom/object.h"
/* Ring buffer chardev */
typedef struct {
struct RingBufChardev {
Chardev parent;
size_t size;
size_t prod;
size_t cons;
uint8_t *cbuf;
} RingBufChardev;
};
typedef struct RingBufChardev RingBufChardev;
#define RINGBUF_CHARDEV(obj) \
OBJECT_CHECK(RingBufChardev, (obj), TYPE_CHARDEV_RINGBUF)

6
chardev/char-socket.c
View File

@ -36,6 +36,7 @@
#include "qapi/qapi-visit-sockets.h"
#include "chardev/char-io.h"
#include "qom/object.h"
/***********************************************************/
/* TCP Net console */
@ -53,7 +54,7 @@ typedef enum {
TCP_CHARDEV_STATE_CONNECTED,
} TCPChardevState;
typedef struct {
struct SocketChardev {
Chardev parent;
QIOChannel *ioc; /* Client I/O channel */
QIOChannelSocket *sioc; /* Client master channel */
@ -84,7 +85,8 @@ typedef struct {
bool connect_err_reported;
QIOTask *connect_task;
} SocketChardev;
};
typedef struct SocketChardev SocketChardev;
#define SOCKET_CHARDEV(obj) \
OBJECT_CHECK(SocketChardev, (obj), TYPE_CHARDEV_SOCKET)

6
chardev/char-udp.c
View File

@ -30,18 +30,20 @@
#include "qemu/option.h"
#include "chardev/char-io.h"
#include "qom/object.h"
/***********************************************************/
/* UDP Net console */
typedef struct {
struct UdpChardev {
Chardev parent;
QIOChannel *ioc;
uint8_t buf[CHR_READ_BUF_LEN];
int bufcnt;
int bufptr;
int max_size;
} UdpChardev;
};
typedef struct UdpChardev UdpChardev;
#define UDP_CHARDEV(obj) OBJECT_CHECK(UdpChardev, (obj), TYPE_CHARDEV_UDP)

6
chardev/char-win-stdio.c
View File

@ -28,15 +28,17 @@
#include "qemu/module.h"
#include "chardev/char-win.h"
#include "chardev/char-win-stdio.h"
#include "qom/object.h"
typedef struct {
struct WinStdioChardev {
Chardev parent;
HANDLE hStdIn;
HANDLE hInputReadyEvent;
HANDLE hInputDoneEvent;
HANDLE hInputThread;
uint8_t win_stdio_buf;
} WinStdioChardev;
};
typedef struct WinStdioChardev WinStdioChardev;
#define WIN_STDIO_CHARDEV(obj) \
OBJECT_CHECK(WinStdioChardev, (obj), TYPE_CHARDEV_WIN_STDIO)

5
chardev/chardev-internal.h
View File

@ -32,7 +32,7 @@
#define MUX_BUFFER_SIZE 32 /* Must be a power of 2. */
#define MUX_BUFFER_MASK (MUX_BUFFER_SIZE - 1)
typedef struct MuxChardev {
struct MuxChardev {
Chardev parent;
CharBackend *backends[MAX_MUX];
CharBackend chr;
@ -51,7 +51,8 @@ typedef struct MuxChardev {
/* Protected by the Chardev chr_write_lock. */
int linestart;
int64_t timestamps_start;
} MuxChardev;
};
typedef struct MuxChardev MuxChardev;
#define MUX_CHARDEV(obj) OBJECT_CHECK(MuxChardev, (obj), TYPE_CHARDEV_MUX)
#define CHARDEV_IS_MUX(chr) \

6
chardev/msmouse.c
View File

@ -27,11 +27,12 @@
#include "chardev/char.h"
#include "ui/console.h"
#include "ui/input.h"
#include "qom/object.h"
#define MSMOUSE_LO6(n) ((n) & 0x3f)
#define MSMOUSE_HI2(n) (((n) & 0xc0) >> 6)
typedef struct {
struct MouseChardev {
Chardev parent;
QemuInputHandlerState *hs;
@ -40,7 +41,8 @@ typedef struct {
bool btnc[INPUT_BUTTON__MAX];
uint8_t outbuf[32];
int outlen;
} MouseChardev;
};
typedef struct MouseChardev MouseChardev;
#define TYPE_CHARDEV_MSMOUSE "chardev-msmouse"
#define MOUSE_CHARDEV(obj) \

6
chardev/testdev.c
View File

@ -27,15 +27,17 @@
#include "qemu/osdep.h"
#include "qemu/module.h"
#include "chardev/char.h"
#include "qom/object.h"
#define BUF_SIZE 32
typedef struct {
struct TestdevChardev {
Chardev parent;
uint8_t in_buf[32];
int in_buf_used;
} TestdevChardev;
};
typedef struct TestdevChardev TestdevChardev;
#define TYPE_CHARDEV_TESTDEV "chardev-testdev"
#define TESTDEV_CHARDEV(obj) \

6
chardev/wctablet.c
View File

@ -32,6 +32,7 @@
#include "ui/console.h"
#include "ui/input.h"
#include "trace.h"
#include "qom/object.h"
#define WC_OUTPUT_BUF_MAX_LEN 512
@ -64,7 +65,7 @@ uint8_t WC_FULL_CONFIG_STRING[WC_FULL_CONFIG_STRING_LENGTH + 1] = {
};
/* This structure is used to save private info for Wacom Tablet. */
typedef struct {
struct TabletChardev {
Chardev parent;
QemuInputHandlerState *hs;
@ -81,7 +82,8 @@ typedef struct {
int axis[INPUT_AXIS__MAX];
bool btns[INPUT_BUTTON__MAX];
} TabletChardev;
};
typedef struct TabletChardev TabletChardev;
#define TYPE_CHARDEV_WCTABLET "chardev-wctablet"
#define WCTABLET_CHARDEV(obj) \

7
hw/9pfs/virtio-9p.h
View File

@ -4,15 +4,16 @@
#include "standard-headers/linux/virtio_9p.h"
#include "hw/virtio/virtio.h"
#include "9p.h"
#include "qom/object.h"
typedef struct V9fsVirtioState
{
struct V9fsVirtioState {
VirtIODevice parent_obj;
VirtQueue *vq;
size_t config_size;
VirtQueueElement *elems[MAX_REQ];
V9fsState state;
} V9fsVirtioState;
};
typedef struct V9fsVirtioState V9fsVirtioState;
#define TYPE_VIRTIO_9P "virtio-9p-device"
#define VIRTIO_9P(obj) \

6
hw/acpi/piix4.c
View File

@ -45,6 +45,7 @@
#include "migration/vmstate.h"
#include "hw/core/cpu.h"
#include "trace.h"
#include "qom/object.h"
#define GPE_BASE 0xafe0
#define GPE_LEN 4
@ -54,7 +55,7 @@ struct pci_status {
uint32_t down;
};
typedef struct PIIX4PMState {
struct PIIX4PMState {
/*< private >*/
PCIDevice parent_obj;
/*< public >*/
@ -89,7 +90,8 @@ typedef struct PIIX4PMState {
CPUHotplugState cpuhp_state;
MemHotplugState acpi_memory_hotplug;
} PIIX4PMState;
};
typedef struct PIIX4PMState PIIX4PMState;
#define PIIX4_PM(obj) \
OBJECT_CHECK(PIIX4PMState, (obj), TYPE_PIIX4_PM)

6
hw/alpha/typhoon.c
View File

@ -15,6 +15,7 @@
#include "hw/irq.h"
#include "alpha_sys.h"
#include "exec/address-spaces.h"
#include "qom/object.h"
#define TYPE_TYPHOON_PCI_HOST_BRIDGE "typhoon-pcihost"
@ -49,16 +50,17 @@ typedef struct TyphoonPchip {
TyphoonWindow win[4];
} TyphoonPchip;
typedef struct TyphoonState TyphoonState;
#define TYPHOON_PCI_HOST_BRIDGE(obj) \
OBJECT_CHECK(TyphoonState, (obj), TYPE_TYPHOON_PCI_HOST_BRIDGE)
typedef struct TyphoonState {
struct TyphoonState {
PCIHostState parent_obj;
TyphoonCchip cchip;
TyphoonPchip pchip;
MemoryRegion dchip_region;
} TyphoonState;
};
/* Called when one of DRIR or DIM changes. */
static void cpu_irq_change(AlphaCPU *cpu, uint64_t req)

6
hw/arm/collie.c
View File

@ -18,12 +18,14 @@
#include "hw/block/flash.h"
#include "exec/address-spaces.h"
#include "cpu.h"
#include "qom/object.h"
typedef struct {
struct CollieMachineState {
MachineState parent;
StrongARMState *sa1110;
} CollieMachineState;
};
typedef struct CollieMachineState CollieMachineState;
#define TYPE_COLLIE_MACHINE MACHINE_TYPE_NAME("collie")
#define COLLIE_MACHINE(obj) \

6
hw/arm/highbank.c
View File

@ -36,6 +36,7 @@
#include "hw/cpu/a9mpcore.h"
#include "hw/cpu/a15mpcore.h"
#include "qemu/log.h"
#include "qom/object.h"
#define SMP_BOOT_ADDR 0x100
#define SMP_BOOT_REG 0x40
@ -155,17 +156,18 @@ static const MemoryRegionOps hb_mem_ops = {
};
#define TYPE_HIGHBANK_REGISTERS "highbank-regs"
typedef struct HighbankRegsState HighbankRegsState;
#define HIGHBANK_REGISTERS(obj) \
OBJECT_CHECK(HighbankRegsState, (obj), TYPE_HIGHBANK_REGISTERS)
typedef struct {
struct HighbankRegsState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
uint32_t regs[NUM_REGS];
} HighbankRegsState;
};
static VMStateDescription vmstate_highbank_regs = {
.name = "highbank-regs",

16
hw/arm/integratorcp.c
View File

@ -26,12 +26,14 @@
#include "hw/hw.h"
#include "hw/irq.h"
#include "hw/sd/sd.h"
#include "qom/object.h"
#define TYPE_INTEGRATOR_CM "integrator_core"
typedef struct IntegratorCMState IntegratorCMState;
#define INTEGRATOR_CM(obj) \
OBJECT_CHECK(IntegratorCMState, (obj), TYPE_INTEGRATOR_CM)
typedef struct IntegratorCMState {
struct IntegratorCMState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
@ -51,7 +53,7 @@ typedef struct IntegratorCMState {
uint32_t int_level;
uint32_t irq_enabled;
uint32_t fiq_enabled;
} IntegratorCMState;
};
static uint8_t integrator_spd[128] = {
128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1,
@ -326,10 +328,11 @@ static void integratorcm_realize(DeviceState *d, Error **errp)
/* Primary interrupt controller. */
#define TYPE_INTEGRATOR_PIC "integrator_pic"
typedef struct icp_pic_state icp_pic_state;
#define INTEGRATOR_PIC(obj) \
OBJECT_CHECK(icp_pic_state, (obj), TYPE_INTEGRATOR_PIC)
typedef struct icp_pic_state {
struct icp_pic_state {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
@ -340,7 +343,7 @@ typedef struct icp_pic_state {
uint32_t fiq_enabled;
qemu_irq parent_irq;
qemu_irq parent_fiq;
} icp_pic_state;
};
static const VMStateDescription vmstate_icp_pic = {
.name = "icp_pic",
@ -465,10 +468,11 @@ static void icp_pic_init(Object *obj)
/* CP control registers. */
#define TYPE_ICP_CONTROL_REGS "icp-ctrl-regs"
typedef struct ICPCtrlRegsState ICPCtrlRegsState;
#define ICP_CONTROL_REGS(obj) \
OBJECT_CHECK(ICPCtrlRegsState, (obj), TYPE_ICP_CONTROL_REGS)
typedef struct ICPCtrlRegsState {
struct ICPCtrlRegsState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
@ -477,7 +481,7 @@ typedef struct ICPCtrlRegsState {
qemu_irq mmc_irq;
uint32_t intreg_state;
} ICPCtrlRegsState;
};
#define ICP_GPIO_MMC_WPROT "mmc-wprot"
#define ICP_GPIO_MMC_CARDIN "mmc-cardin"

6
hw/arm/microbit.c
View File

@ -18,13 +18,15 @@
#include "hw/arm/nrf51_soc.h"
#include "hw/i2c/microbit_i2c.h"
#include "hw/qdev-properties.h"
#include "qom/object.h"
typedef struct {
struct MicrobitMachineState {
MachineState parent;
NRF51State nrf51;
MicrobitI2CState i2c;
} MicrobitMachineState;
};
typedef struct MicrobitMachineState MicrobitMachineState;
#define TYPE_MICROBIT_MACHINE MACHINE_TYPE_NAME("microbit")

11
hw/arm/mps2-tz.c
View File

@ -62,6 +62,7 @@
#include "hw/net/lan9118.h"
#include "net/net.h"
#include "hw/core/split-irq.h"
#include "qom/object.h"
#define MPS2TZ_NUMIRQ 92
@ -70,14 +71,15 @@ typedef enum MPS2TZFPGAType {
FPGA_AN521,
} MPS2TZFPGAType;
typedef struct {
struct MPS2TZMachineClass {
MachineClass parent;
MPS2TZFPGAType fpga_type;
uint32_t scc_id;
const char *armsse_type;
} MPS2TZMachineClass;
};
typedef struct MPS2TZMachineClass MPS2TZMachineClass;
typedef struct {
struct MPS2TZMachineState {
MachineState parent;
ARMSSE iotkit;
@ -99,7 +101,8 @@ typedef struct {
qemu_or_irq uart_irq_orgate;
DeviceState *lan9118;
SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ];
} MPS2TZMachineState;
};
typedef struct MPS2TZMachineState MPS2TZMachineState;
#define TYPE_MPS2TZ_MACHINE "mps2tz"
#define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505")

11
hw/arm/mps2.c
View File

@ -44,19 +44,21 @@
#include "hw/net/lan9118.h"
#include "net/net.h"
#include "hw/watchdog/cmsdk-apb-watchdog.h"
#include "qom/object.h"
typedef enum MPS2FPGAType {
FPGA_AN385,
FPGA_AN511,
} MPS2FPGAType;
typedef struct {
struct MPS2MachineClass {
MachineClass parent;
MPS2FPGAType fpga_type;
uint32_t scc_id;
} MPS2MachineClass;
};
typedef struct MPS2MachineClass MPS2MachineClass;
typedef struct {
struct MPS2MachineState {
MachineState parent;
ARMv7MState armv7m;
@ -75,7 +77,8 @@ typedef struct {
/* CMSDK APB subsystem */
CMSDKAPBDualTimer dualtimer;
CMSDKAPBWatchdog watchdog;
} MPS2MachineState;
};
typedef struct MPS2MachineState MPS2MachineState;
#define TYPE_MPS2_MACHINE "mps2"
#define TYPE_MPS2_AN385_MACHINE MACHINE_TYPE_NAME("mps2-an385")

11
hw/arm/musca.c
View File

@ -33,6 +33,7 @@
#include "hw/misc/tz-ppc.h"
#include "hw/misc/unimp.h"
#include "hw/rtc/pl031.h"
#include "qom/object.h"
#define MUSCA_NUMIRQ_MAX 96
#define MUSCA_PPC_MAX 3
@ -45,7 +46,7 @@ typedef enum MuscaType {
MUSCA_B1,
} MuscaType;
typedef struct {
struct MuscaMachineClass {
MachineClass parent;
MuscaType type;
uint32_t init_svtor;
@ -53,9 +54,10 @@ typedef struct {
int num_irqs;
const MPCInfo *mpc_info;
int num_mpcs;
} MuscaMachineClass;
};
typedef struct MuscaMachineClass MuscaMachineClass;
typedef struct {
struct MuscaMachineState {
MachineState parent;
ARMSSE sse;
@ -81,7 +83,8 @@ typedef struct {
UnimplementedDeviceState sdio;
UnimplementedDeviceState gpio;
UnimplementedDeviceState cryptoisland;
} MuscaMachineState;
};
typedef struct MuscaMachineState MuscaMachineState;
#define TYPE_MUSCA_MACHINE "musca"
#define TYPE_MUSCA_A_MACHINE MACHINE_TYPE_NAME("musca-a")

41
hw/arm/musicpal.c
View File

@ -34,6 +34,7 @@
#include "exec/address-spaces.h"
#include "ui/pixel_ops.h"
#include "qemu/cutils.h"
#include "qom/object.h"
#define MP_MISC_BASE 0x80002000
#define MP_MISC_SIZE 0x00001000
@ -154,10 +155,11 @@ typedef struct mv88w8618_rx_desc {
} mv88w8618_rx_desc;
#define TYPE_MV88W8618_ETH "mv88w8618_eth"
typedef struct mv88w8618_eth_state mv88w8618_eth_state;
#define MV88W8618_ETH(obj) \
OBJECT_CHECK(mv88w8618_eth_state, (obj), TYPE_MV88W8618_ETH)
typedef struct mv88w8618_eth_state {
struct mv88w8618_eth_state {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
@ -177,7 +179,7 @@ typedef struct mv88w8618_eth_state {
uint32_t cur_rx[4];
NICState *nic;
NICConf conf;
} mv88w8618_eth_state;
};
static void eth_rx_desc_put(AddressSpace *dma_as, uint32_t addr,
mv88w8618_rx_desc *desc)
@ -483,10 +485,11 @@ static const TypeInfo mv88w8618_eth_info = {
#define MP_LCD_TEXTCOLOR 0xe0e0ff /* RRGGBB */
#define TYPE_MUSICPAL_LCD "musicpal_lcd"
typedef struct musicpal_lcd_state musicpal_lcd_state;
#define MUSICPAL_LCD(obj) \
OBJECT_CHECK(musicpal_lcd_state, (obj), TYPE_MUSICPAL_LCD)
typedef struct musicpal_lcd_state {
struct musicpal_lcd_state {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
@ -499,7 +502,7 @@ typedef struct musicpal_lcd_state {
uint32_t page_off;
QemuConsole *con;
uint8_t video_ram[128*64/8];
} musicpal_lcd_state;
};
static uint8_t scale_lcd_color(musicpal_lcd_state *s, uint8_t col)
{
@ -700,10 +703,11 @@ static const TypeInfo musicpal_lcd_info = {
#define MP_PIC_ENABLE_CLR 0x0C
#define TYPE_MV88W8618_PIC "mv88w8618_pic"
typedef struct mv88w8618_pic_state mv88w8618_pic_state;
#define MV88W8618_PIC(obj) \
OBJECT_CHECK(mv88w8618_pic_state, (obj), TYPE_MV88W8618_PIC)
typedef struct mv88w8618_pic_state {
struct mv88w8618_pic_state {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
@ -712,7 +716,7 @@ typedef struct mv88w8618_pic_state {
uint32_t level;
uint32_t enabled;
qemu_irq parent_irq;
} mv88w8618_pic_state;
};
static void mv88w8618_pic_update(mv88w8618_pic_state *s)
{
@ -837,17 +841,18 @@ typedef struct mv88w8618_timer_state {
} mv88w8618_timer_state;
#define TYPE_MV88W8618_PIT "mv88w8618_pit"
typedef struct mv88w8618_pit_state mv88w8618_pit_state;
#define MV88W8618_PIT(obj) \
OBJECT_CHECK(mv88w8618_pit_state, (obj), TYPE_MV88W8618_PIT)
typedef struct mv88w8618_pit_state {
struct mv88w8618_pit_state {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
mv88w8618_timer_state timer[4];
} mv88w8618_pit_state;
};
static void mv88w8618_timer_tick(void *opaque)
{
@ -1004,17 +1009,18 @@ static const TypeInfo mv88w8618_pit_info = {
#define MP_FLASHCFG_CFGR0 0x04
#define TYPE_MV88W8618_FLASHCFG "mv88w8618_flashcfg"
typedef struct mv88w8618_flashcfg_state mv88w8618_flashcfg_state;
#define MV88W8618_FLASHCFG(obj) \
OBJECT_CHECK(mv88w8618_flashcfg_state, (obj), TYPE_MV88W8618_FLASHCFG)
typedef struct mv88w8618_flashcfg_state {
struct mv88w8618_flashcfg_state {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
uint32_t cfgr0;
} mv88w8618_flashcfg_state;
};
static uint64_t mv88w8618_flashcfg_read(void *opaque,
hwaddr offset,
@ -1090,10 +1096,11 @@ static const TypeInfo mv88w8618_flashcfg_info = {
#define MP_BOARD_REVISION 0x31
typedef struct {
struct MusicPalMiscState {
SysBusDevice parent_obj;
MemoryRegion iomem;
} MusicPalMiscState;
};
typedef struct MusicPalMiscState MusicPalMiscState;
#define TYPE_MUSICPAL_MISC "musicpal-misc"
#define MUSICPAL_MISC(obj) \
@ -1202,10 +1209,11 @@ static void mv88w8618_wlan_realize(DeviceState *dev, Error **errp)
#define MP_OE_LCD_BRIGHTNESS 0x0007
#define TYPE_MUSICPAL_GPIO "musicpal_gpio"
typedef struct musicpal_gpio_state musicpal_gpio_state;
#define MUSICPAL_GPIO(obj) \
OBJECT_CHECK(musicpal_gpio_state, (obj), TYPE_MUSICPAL_GPIO)
typedef struct musicpal_gpio_state {
struct musicpal_gpio_state {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
@ -1219,7 +1227,7 @@ typedef struct musicpal_gpio_state {
uint32_t isr;
qemu_irq irq;
qemu_irq out[5]; /* 3 brightness out + 2 lcd (data and clock ) */
} musicpal_gpio_state;
};
static void musicpal_gpio_brightness_update(musicpal_gpio_state *s) {
int i;
@ -1452,10 +1460,11 @@ static const TypeInfo musicpal_gpio_info = {
#define MP_KEY_BTN_NAVIGATION (1 << 7)
#define TYPE_MUSICPAL_KEY "musicpal_key"
typedef struct musicpal_key_state musicpal_key_state;
#define MUSICPAL_KEY(obj) \
OBJECT_CHECK(musicpal_key_state, (obj), TYPE_MUSICPAL_KEY)
typedef struct musicpal_key_state {
struct musicpal_key_state {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
@ -1464,7 +1473,7 @@ typedef struct musicpal_key_state {
uint32_t kbd_extended;
uint32_t pressed_keys;
qemu_irq out[8];
} musicpal_key_state;
};
static void musicpal_key_event(void *opaque, int keycode)
{

6
hw/arm/palm.c
View File

@ -32,6 +32,7 @@
#include "exec/address-spaces.h"
#include "cpu.h"
#include "qemu/cutils.h"
#include "qom/object.h"
static uint64_t static_read(void *opaque, hwaddr offset, unsigned size)
{
@ -132,12 +133,13 @@ static void palmte_button_event(void *opaque, int keycode)
*/
#define TYPE_PALM_MISC_GPIO "palm-misc-gpio"
typedef struct PalmMiscGPIOState PalmMiscGPIOState;
#define PALM_MISC_GPIO(obj) \
OBJECT_CHECK(PalmMiscGPIOState, (obj), TYPE_PALM_MISC_GPIO)
typedef struct PalmMiscGPIOState {
struct PalmMiscGPIOState {
SysBusDevice parent_obj;
} PalmMiscGPIOState;
};
static void palmte_onoff_gpios(void *opaque, int line, int level)
{

16
hw/arm/pxa2xx.c
View File

@ -28,6 +28,7 @@
#include "sysemu/qtest.h"
#include "qemu/cutils.h"
#include "qemu/log.h"
#include "qom/object.h"
static struct {
hwaddr io_base;
@ -469,11 +470,12 @@ static const VMStateDescription vmstate_pxa2xx_mm = {
};
#define TYPE_PXA2XX_SSP "pxa2xx-ssp"
typedef struct PXA2xxSSPState PXA2xxSSPState;
#define PXA2XX_SSP(obj) \
OBJECT_CHECK(PXA2xxSSPState, (obj), TYPE_PXA2XX_SSP)
/* Synchronous Serial Ports */
typedef struct {
struct PXA2xxSSPState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
@ -495,7 +497,7 @@ typedef struct {
uint32_t rx_fifo[16];
uint32_t rx_level;
uint32_t rx_start;
} PXA2xxSSPState;
};
static bool pxa2xx_ssp_vmstate_validate(void *opaque, int version_id)
{
@ -809,10 +811,11 @@ static void pxa2xx_ssp_init(Object *obj)
#define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */
#define TYPE_PXA2XX_RTC "pxa2xx_rtc"
typedef struct PXA2xxRTCState PXA2xxRTCState;
#define PXA2XX_RTC(obj) \
OBJECT_CHECK(PXA2xxRTCState, (obj), TYPE_PXA2XX_RTC)
typedef struct {
struct PXA2xxRTCState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
@ -843,7 +846,7 @@ typedef struct {
QEMUTimer *rtc_swal2;
QEMUTimer *rtc_pi;
qemu_irq rtc_irq;
} PXA2xxRTCState;
};
static inline void pxa2xx_rtc_int_update(PXA2xxRTCState *s)
{
@ -1242,14 +1245,15 @@ static const TypeInfo pxa2xx_rtc_sysbus_info = {
/* I2C Interface */
#define TYPE_PXA2XX_I2C_SLAVE "pxa2xx-i2c-slave"
typedef struct PXA2xxI2CSlaveState PXA2xxI2CSlaveState;
#define PXA2XX_I2C_SLAVE(obj) \
OBJECT_CHECK(PXA2xxI2CSlaveState, (obj), TYPE_PXA2XX_I2C_SLAVE)
typedef struct PXA2xxI2CSlaveState {
struct PXA2xxI2CSlaveState {
I2CSlave parent_obj;
PXA2xxI2CState *host;
} PXA2xxI2CSlaveState;
};
struct PXA2xxI2CState {
/*< private >*/

3
hw/arm/pxa2xx_gpio.c
View File

@ -17,14 +17,15 @@
#include "qapi/error.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "qom/object.h"
#define PXA2XX_GPIO_BANKS 4
#define TYPE_PXA2XX_GPIO "pxa2xx-gpio"
typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo;
#define PXA2XX_GPIO(obj) \
OBJECT_CHECK(PXA2xxGPIOInfo, (obj), TYPE_PXA2XX_GPIO)
typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo;
struct PXA2xxGPIOInfo {
/*< private >*/
SysBusDevice parent_obj;

6
hw/arm/pxa2xx_pic.c
View File

@ -16,6 +16,7 @@
#include "hw/arm/pxa.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "qom/object.h"
#define ICIP 0x00 /* Interrupt Controller IRQ Pending register */
#define ICMR 0x04 /* Interrupt Controller Mask register */
@ -37,10 +38,11 @@
#define PXA2XX_PIC_SRCS 40
#define TYPE_PXA2XX_PIC "pxa2xx_pic"
typedef struct PXA2xxPICState PXA2xxPICState;
#define PXA2XX_PIC(obj) \
OBJECT_CHECK(PXA2xxPICState, (obj), TYPE_PXA2XX_PIC)
typedef struct {
struct PXA2xxPICState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
@ -52,7 +54,7 @@ typedef struct {
uint32_t is_fiq[2];
uint32_t int_idle;
uint32_t priority[PXA2XX_PIC_SRCS];
} PXA2xxPICState;
};
static void pxa2xx_pic_update(void *opaque)
{

11
hw/arm/raspi.c
View File

@ -24,6 +24,7 @@
#include "hw/loader.h"
#include "hw/arm/boot.h"
#include "sysemu/sysemu.h"
#include "qom/object.h"
#define SMPBOOT_ADDR 0x300 /* this should leave enough space for ATAGS */
#define MVBAR_ADDR 0x400 /* secure vectors */
@ -35,19 +36,21 @@
/* Registered machine type (matches RPi Foundation bootloader and U-Boot) */
#define MACH_TYPE_BCM2708 3138
typedef struct RaspiMachineState {
struct RaspiMachineState {
/*< private >*/
MachineState parent_obj;
/*< public >*/
BCM283XState soc;
} RaspiMachineState;
};
typedef struct RaspiMachineState RaspiMachineState;
typedef struct RaspiMachineClass {
struct RaspiMachineClass {
/*< private >*/
MachineClass parent_obj;
/*< public >*/
uint32_t board_rev;
} RaspiMachineClass;
};
typedef struct RaspiMachineClass RaspiMachineClass;
#define TYPE_RASPI_MACHINE MACHINE_TYPE_NAME("raspi-common")
#define RASPI_MACHINE(obj) \

6
hw/arm/sbsa-ref.c
View File

@ -41,6 +41,7 @@
#include "hw/usb.h"
#include "hw/char/pl011.h"
#include "net/net.h"
#include "qom/object.h"
#define RAMLIMIT_GB 8192
#define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB)
@ -84,7 +85,7 @@ typedef struct MemMapEntry {
hwaddr size;
} MemMapEntry;
typedef struct {
struct SBSAMachineState {
MachineState parent;
struct arm_boot_info bootinfo;
int smp_cpus;
@ -93,7 +94,8 @@ typedef struct {
int psci_conduit;
DeviceState *gic;
PFlashCFI01 *flash[2];
} SBSAMachineState;
};
typedef struct SBSAMachineState SBSAMachineState;
#define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref")
#define SBSA_MACHINE(obj) \

36
hw/arm/spitz.c
View File

@ -34,16 +34,18 @@
#include "migration/vmstate.h"
#include "exec/address-spaces.h"
#include "cpu.h"
#include "qom/object.h"
enum spitz_model_e { spitz, akita, borzoi, terrier };
typedef struct {
struct SpitzMachineClass {
MachineClass parent;
enum spitz_model_e model;
int arm_id;
} SpitzMachineClass;
};
typedef struct SpitzMachineClass SpitzMachineClass;
typedef struct {
struct SpitzMachineState {
MachineState parent;
PXA2xxState *mpu;
DeviceState *mux;
@ -53,7 +55,8 @@ typedef struct {
DeviceState *scp0;
DeviceState *scp1;
DeviceState *misc_gpio;
} SpitzMachineState;
};
typedef struct SpitzMachineState SpitzMachineState;
#define TYPE_SPITZ_MACHINE "spitz-common"
#define SPITZ_MACHINE(obj) \
@ -85,9 +88,10 @@ typedef struct {
#define FLASHCTL_NCE (FLASHCTL_CE0 | FLASHCTL_CE1)
#define TYPE_SL_NAND "sl-nand"
typedef struct SLNANDState SLNANDState;
#define SL_NAND(obj) OBJECT_CHECK(SLNANDState, (obj), TYPE_SL_NAND)
typedef struct {
struct SLNANDState {
SysBusDevice parent_obj;
MemoryRegion iomem;
@ -96,7 +100,7 @@ typedef struct {
uint8_t manf_id;
uint8_t chip_id;
ECCState ecc;
} SLNANDState;
};
static uint64_t sl_read(void *opaque, hwaddr addr, unsigned size)
{
@ -261,10 +265,11 @@ static const int spitz_gpiomap[5] = {
};
#define TYPE_SPITZ_KEYBOARD "spitz-keyboard"
typedef struct SpitzKeyboardState SpitzKeyboardState;
#define SPITZ_KEYBOARD(obj) \
OBJECT_CHECK(SpitzKeyboardState, (obj), TYPE_SPITZ_KEYBOARD)
typedef struct {
struct SpitzKeyboardState {
SysBusDevice parent_obj;
qemu_irq sense[SPITZ_KEY_SENSE_NUM];
@ -280,7 +285,7 @@ typedef struct {
uint8_t fifo[16];
int fifopos, fifolen;
QEMUTimer *kbdtimer;
} SpitzKeyboardState;
};
static void spitz_keyboard_sense_update(SpitzKeyboardState *s)
{
@ -580,13 +585,14 @@ static void spitz_keyboard_realize(DeviceState *dev, Error **errp)
#define LCDTG_POLCTRL 0x07
#define TYPE_SPITZ_LCDTG "spitz-lcdtg"
typedef struct SpitzLCDTG SpitzLCDTG;
#define SPITZ_LCDTG(obj) OBJECT_CHECK(SpitzLCDTG, (obj), TYPE_SPITZ_LCDTG)
typedef struct {
struct SpitzLCDTG {
SSISlave ssidev;
uint32_t bl_intensity;
uint32_t bl_power;
} SpitzLCDTG;
};
static void spitz_bl_update(SpitzLCDTG *s)
{
@ -668,14 +674,15 @@ static void spitz_lcdtg_realize(SSISlave *ssi, Error **errp)
#define SPITZ_GPIO_TP_INT 11
#define TYPE_CORGI_SSP "corgi-ssp"
typedef struct CorgiSSPState CorgiSSPState;
#define CORGI_SSP(obj) OBJECT_CHECK(CorgiSSPState, (obj), TYPE_CORGI_SSP)
/* "Demux" the signal based on current chipselect */
typedef struct {
struct CorgiSSPState {
SSISlave ssidev;
SSIBus *bus[3];
uint32_t enable[3];
} CorgiSSPState;
};
static uint32_t corgi_ssp_transfer(SSISlave *dev, uint32_t value)
{
@ -819,14 +826,15 @@ static void spitz_akita_i2c_setup(PXA2xxState *cpu)
* + named GPIO output "adc-temp": the ADC value, to be wired up to the max111x
*/
#define TYPE_SPITZ_MISC_GPIO "spitz-misc-gpio"
typedef struct SpitzMiscGPIOState SpitzMiscGPIOState;
#define SPITZ_MISC_GPIO(obj) \
OBJECT_CHECK(SpitzMiscGPIOState, (obj), TYPE_SPITZ_MISC_GPIO)
typedef struct SpitzMiscGPIOState {
struct SpitzMiscGPIOState {
SysBusDevice parent_obj;
qemu_irq adc_value;
} SpitzMiscGPIOState;
};
static void spitz_misc_charging(void *opaque, int n, int level)
{

16
hw/arm/stellaris.c
View File

@ -27,6 +27,7 @@
#include "migration/vmstate.h"
#include "hw/misc/unimp.h"
#include "cpu.h"
#include "qom/object.h"
#define GPIO_A 0
#define GPIO_B 1
@ -57,10 +58,11 @@ typedef const struct {
/* General purpose timer module. */
#define TYPE_STELLARIS_GPTM "stellaris-gptm"
typedef struct gptm_state gptm_state;
#define STELLARIS_GPTM(obj) \
OBJECT_CHECK(gptm_state, (obj), TYPE_STELLARIS_GPTM)
typedef struct gptm_state {
struct gptm_state {
SysBusDevice parent_obj;
MemoryRegion iomem;
@ -80,7 +82,7 @@ typedef struct gptm_state {
/* The timers have an alternate output used to trigger the ADC. */
qemu_irq trigger;
qemu_irq irq;
} gptm_state;
};
static void gptm_update_irq(gptm_state *s)
{
@ -719,10 +721,11 @@ static int stellaris_sys_init(uint32_t base, qemu_irq irq,
/* I2C controller. */
#define TYPE_STELLARIS_I2C "stellaris-i2c"
typedef struct stellaris_i2c_state stellaris_i2c_state;
#define STELLARIS_I2C(obj) \
OBJECT_CHECK(stellaris_i2c_state, (obj), TYPE_STELLARIS_I2C)
typedef struct {
struct stellaris_i2c_state {
SysBusDevice parent_obj;
I2CBus *bus;
@ -735,7 +738,7 @@ typedef struct {
uint32_t mimr;
uint32_t mris;
uint32_t mcr;
} stellaris_i2c_state;
};
#define STELLARIS_I2C_MCS_BUSY 0x01
#define STELLARIS_I2C_MCS_ERROR 0x02
@ -932,10 +935,11 @@ static void stellaris_i2c_init(Object *obj)
#define STELLARIS_ADC_FIFO_FULL 0x1000
#define TYPE_STELLARIS_ADC "stellaris-adc"
typedef struct StellarisADCState stellaris_adc_state;
#define STELLARIS_ADC(obj) \
OBJECT_CHECK(stellaris_adc_state, (obj), TYPE_STELLARIS_ADC)
typedef struct StellarisADCState {
struct StellarisADCState {
SysBusDevice parent_obj;
MemoryRegion iomem;
@ -955,7 +959,7 @@ typedef struct StellarisADCState {
uint32_t ssctl[4];
uint32_t noise;
qemu_irq irq[4];
} stellaris_adc_state;
};
static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n)
{

25
hw/arm/strongarm.c
View File

@ -45,6 +45,7 @@
#include "qapi/error.h"
#include "qemu/cutils.h"
#include "qemu/log.h"
#include "qom/object.h"
//#define DEBUG
@ -84,10 +85,11 @@ static struct {
/* Interrupt Controller */
#define TYPE_STRONGARM_PIC "strongarm_pic"
typedef struct StrongARMPICState StrongARMPICState;
#define STRONGARM_PIC(obj) \
OBJECT_CHECK(StrongARMPICState, (obj), TYPE_STRONGARM_PIC)
typedef struct StrongARMPICState {
struct StrongARMPICState {
SysBusDevice parent_obj;
MemoryRegion iomem;
@ -98,7 +100,7 @@ typedef struct StrongARMPICState {
uint32_t enabled;
uint32_t is_fiq;
uint32_t int_idle;
} StrongARMPICState;
};
#define ICIP 0x00
#define ICMR 0x04
@ -252,10 +254,11 @@ static const TypeInfo strongarm_pic_info = {
* f = 32 768 / (RTTR_trim + 1) */
#define TYPE_STRONGARM_RTC "strongarm-rtc"
typedef struct StrongARMRTCState StrongARMRTCState;
#define STRONGARM_RTC(obj) \
OBJECT_CHECK(StrongARMRTCState, (obj), TYPE_STRONGARM_RTC)
typedef struct StrongARMRTCState {
struct StrongARMRTCState {
SysBusDevice parent_obj;
MemoryRegion iomem;
@ -268,7 +271,7 @@ typedef struct StrongARMRTCState {
QEMUTimer *rtc_hz;
qemu_irq rtc_irq;
qemu_irq rtc_hz_irq;
} StrongARMRTCState;
};
static inline void strongarm_rtc_int_update(StrongARMRTCState *s)
{
@ -478,10 +481,10 @@ static const TypeInfo strongarm_rtc_sysbus_info = {
#define GAFR 0x1c
#define TYPE_STRONGARM_GPIO "strongarm-gpio"
typedef struct StrongARMGPIOInfo StrongARMGPIOInfo;
#define STRONGARM_GPIO(obj) \
OBJECT_CHECK(StrongARMGPIOInfo, (obj), TYPE_STRONGARM_GPIO)
typedef struct StrongARMGPIOInfo StrongARMGPIOInfo;
struct StrongARMGPIOInfo {
SysBusDevice busdev;
MemoryRegion iomem;
@ -717,10 +720,10 @@ static const TypeInfo strongarm_gpio_info = {
#define PPFR 0x10
#define TYPE_STRONGARM_PPC "strongarm-ppc"
typedef struct StrongARMPPCInfo StrongARMPPCInfo;
#define STRONGARM_PPC(obj) \
OBJECT_CHECK(StrongARMPPCInfo, (obj), TYPE_STRONGARM_PPC)
typedef struct StrongARMPPCInfo StrongARMPPCInfo;
struct StrongARMPPCInfo {
SysBusDevice parent_obj;
@ -918,10 +921,11 @@ static const TypeInfo strongarm_ppc_info = {
#define RX_FIFO_ROR (1 << 10)
#define TYPE_STRONGARM_UART "strongarm-uart"
typedef struct StrongARMUARTState StrongARMUARTState;
#define STRONGARM_UART(obj) \
OBJECT_CHECK(StrongARMUARTState, (obj), TYPE_STRONGARM_UART)
typedef struct StrongARMUARTState {
struct StrongARMUARTState {
SysBusDevice parent_obj;
MemoryRegion iomem;
@ -945,7 +949,7 @@ typedef struct StrongARMUARTState {
bool wait_break_end;
QEMUTimer *rx_timeout_timer;
QEMUTimer *tx_timer;
} StrongARMUARTState;
};
static void strongarm_uart_update_status(StrongARMUARTState *s)
{
@ -1349,10 +1353,11 @@ static const TypeInfo strongarm_uart_info = {
/* Synchronous Serial Ports */
#define TYPE_STRONGARM_SSP "strongarm-ssp"
typedef struct StrongARMSSPState StrongARMSSPState;
#define STRONGARM_SSP(obj) \
OBJECT_CHECK(StrongARMSSPState, (obj), TYPE_STRONGARM_SSP)
typedef struct StrongARMSSPState {
struct StrongARMSSPState {
SysBusDevice parent_obj;
MemoryRegion iomem;
@ -1365,7 +1370,7 @@ typedef struct StrongARMSSPState {
uint16_t rx_fifo[8];
uint8_t rx_level;
uint8_t rx_start;
} StrongARMSSPState;
};
#define SSCR0 0x60 /* SSP Control register 0 */
#define SSCR1 0x64 /* SSP Control register 1 */

11
hw/arm/tosa.c
View File

@ -25,6 +25,7 @@
#include "hw/ssi/ssi.h"
#include "hw/sysbus.h"
#include "exec/address-spaces.h"
#include "qom/object.h"
#define TOSA_RAM 0x04000000
#define TOSA_ROM 0x00800000
@ -74,12 +75,13 @@ static void tosa_microdrive_attach(PXA2xxState *cpu)
*/
#define TYPE_TOSA_MISC_GPIO "tosa-misc-gpio"
typedef struct TosaMiscGPIOState TosaMiscGPIOState;
#define TOSA_MISC_GPIO(obj) \
OBJECT_CHECK(TosaMiscGPIOState, (obj), TYPE_TOSA_MISC_GPIO)
typedef struct TosaMiscGPIOState {
struct TosaMiscGPIOState {
SysBusDevice parent_obj;
} TosaMiscGPIOState;
};
static void tosa_gpio_leds(void *opaque, int line, int level)
{
@ -170,14 +172,15 @@ static void tosa_ssp_realize(SSISlave *dev, Error **errp)
}
#define TYPE_TOSA_DAC "tosa_dac"
typedef struct TosaDACState TosaDACState;
#define TOSA_DAC(obj) OBJECT_CHECK(TosaDACState, (obj), TYPE_TOSA_DAC)
typedef struct {
struct TosaDACState {
I2CSlave parent_obj;
int len;
char buf[3];
} TosaDACState;
};
static int tosa_dac_send(I2CSlave *i2c, uint8_t data)
{

6
hw/arm/versatilepb.c
View File

@ -26,6 +26,7 @@
#include "qemu/error-report.h"
#include "hw/char/pl011.h"
#include "hw/sd/sd.h"
#include "qom/object.h"
#define VERSATILE_FLASH_ADDR 0x34000000
#define VERSATILE_FLASH_SIZE (64 * 1024 * 1024)
@ -34,10 +35,11 @@
/* Primary interrupt controller. */
#define TYPE_VERSATILE_PB_SIC "versatilepb_sic"
typedef struct vpb_sic_state vpb_sic_state;
#define VERSATILE_PB_SIC(obj) \
OBJECT_CHECK(vpb_sic_state, (obj), TYPE_VERSATILE_PB_SIC)
typedef struct vpb_sic_state {
struct vpb_sic_state {
SysBusDevice parent_obj;
MemoryRegion iomem;
@ -46,7 +48,7 @@ typedef struct vpb_sic_state {
uint32_t pic_enable;
qemu_irq parent[32];
int irq;
} vpb_sic_state;
};
static const VMStateDescription vmstate_vpb_sic = {
.name = "versatilepb_sic",

11
hw/arm/vexpress.c
View File

@ -44,6 +44,7 @@
#include "hw/cpu/a15mpcore.h"
#include "hw/i2c/arm_sbcon_i2c.h"
#include "hw/sd/sd.h"
#include "qom/object.h"
#define VEXPRESS_BOARD_ID 0x8e0
#define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024)
@ -166,16 +167,18 @@ static hwaddr motherboard_aseries_map[] = {
typedef struct VEDBoardInfo VEDBoardInfo;
typedef struct {
struct VexpressMachineClass {
MachineClass parent;
VEDBoardInfo *daughterboard;
} VexpressMachineClass;
};
typedef struct VexpressMachineClass VexpressMachineClass;
typedef struct {
struct VexpressMachineState {
MachineState parent;
bool secure;
bool virt;
} VexpressMachineState;
};
typedef struct VexpressMachineState VexpressMachineState;
#define TYPE_VEXPRESS_MACHINE "vexpress"
#define TYPE_VEXPRESS_A9_MACHINE MACHINE_TYPE_NAME("vexpress-a9")

6
hw/arm/xilinx_zynq.c
View File

@ -37,8 +37,10 @@
#include "hw/cpu/a9mpcore.h"
#include "hw/qdev-clock.h"
#include "sysemu/reset.h"
#include "qom/object.h"
#define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9")
typedef struct ZynqMachineState ZynqMachineState;
#define ZYNQ_MACHINE(obj) \
OBJECT_CHECK(ZynqMachineState, (obj), TYPE_ZYNQ_MACHINE)
@ -84,10 +86,10 @@ static const int dma_irqs[8] = {
0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \
0xe5801000 + (addr)
typedef struct ZynqMachineState {
struct ZynqMachineState {
MachineState parent;
Clock *ps_clk;
} ZynqMachineState;
};
static void zynq_write_board_setup(ARMCPU *cpu,
const struct arm_boot_info *info)

6
hw/arm/xlnx-versal-virt.c
View File

@ -22,12 +22,14 @@
#include "cpu.h"
#include "hw/qdev-properties.h"
#include "hw/arm/xlnx-versal.h"
#include "qom/object.h"
#define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt")
typedef struct VersalVirt VersalVirt;
#define XLNX_VERSAL_VIRT_MACHINE(obj) \
OBJECT_CHECK(VersalVirt, (obj), TYPE_XLNX_VERSAL_VIRT_MACHINE)
typedef struct VersalVirt {
struct VersalVirt {
MachineState parent_obj;
Versal soc;
@ -45,7 +47,7 @@ typedef struct VersalVirt {
struct {
bool secure;
} cfg;
} VersalVirt;
};
static void fdt_create(VersalVirt *s)
{

6
hw/arm/xlnx-zcu102.c
View File

@ -24,8 +24,9 @@
#include "qemu/log.h"
#include "sysemu/qtest.h"
#include "sysemu/device_tree.h"
#include "qom/object.h"
typedef struct XlnxZCU102 {
struct XlnxZCU102 {
MachineState parent_obj;
XlnxZynqMPState soc;
@ -34,7 +35,8 @@ typedef struct XlnxZCU102 {
bool virt;
struct arm_boot_info binfo;
} XlnxZCU102;
};
typedef struct XlnxZCU102 XlnxZCU102;
#define TYPE_ZCU102_MACHINE MACHINE_TYPE_NAME("xlnx-zcu102")
#define ZCU102_MACHINE(obj) \

11
hw/arm/z2.c
View File

@ -26,6 +26,7 @@
#include "exec/address-spaces.h"
#include "sysemu/qtest.h"
#include "cpu.h"
#include "qom/object.h"
#ifdef DEBUG_Z2
#define DPRINTF(fmt, ...) \
@ -102,14 +103,15 @@ static struct arm_boot_info z2_binfo = {
#define Z2_GPIO_KEY_ON 1
#define Z2_GPIO_LCD_CS 88
typedef struct {
struct ZipitLCD {
SSISlave ssidev;
int32_t selected;
int32_t enabled;
uint8_t buf[3];
uint32_t cur_reg;
int pos;
} ZipitLCD;
};
typedef struct ZipitLCD ZipitLCD;
#define TYPE_ZIPIT_LCD "zipit-lcd"
#define ZIPIT_LCD(obj) OBJECT_CHECK(ZipitLCD, (obj), TYPE_ZIPIT_LCD)
@ -195,14 +197,15 @@ static const TypeInfo zipit_lcd_info = {
};
#define TYPE_AER915 "aer915"
typedef struct AER915State AER915State;
#define AER915(obj) OBJECT_CHECK(AER915State, (obj), TYPE_AER915)
typedef struct AER915State {
struct AER915State {
I2CSlave parent_obj;
int len;
uint8_t buf[3];
} AER915State;
};
static int aer915_send(I2CSlave *i2c, uint8_t data)
{

6
hw/audio/ac97.c
View File

@ -25,6 +25,7 @@
#include "migration/vmstate.h"
#include "qemu/module.h"
#include "sysemu/dma.h"
#include "qom/object.h"
enum {
AC97_Reset = 0x00,
@ -126,6 +127,7 @@ enum {
#define MUTE_SHIFT 15
#define TYPE_AC97 "AC97"
typedef struct AC97LinkState AC97LinkState;
#define AC97(obj) \
OBJECT_CHECK(AC97LinkState, (obj), TYPE_AC97)
@ -158,7 +160,7 @@ typedef struct AC97BusMasterRegs {
BD bd;
} AC97BusMasterRegs;
typedef struct AC97LinkState {
struct AC97LinkState {
PCIDevice dev;
QEMUSoundCard card;
uint32_t glob_cnt;
@ -175,7 +177,7 @@ typedef struct AC97LinkState {
int bup_flag;
MemoryRegion io_nam;
MemoryRegion io_nabm;
} AC97LinkState;
};
enum {
BUP_SET = 1,

6
hw/audio/adlib.c
View File

@ -29,6 +29,7 @@
#include "audio/audio.h"
#include "hw/isa/isa.h"
#include "hw/qdev-properties.h"
#include "qom/object.h"
//#define DEBUG
@ -51,9 +52,10 @@
#define SHIFT 1
#define TYPE_ADLIB "adlib"
typedef struct AdlibState AdlibState;
#define ADLIB(obj) OBJECT_CHECK(AdlibState, (obj), TYPE_ADLIB)
typedef struct {
struct AdlibState {
ISADevice parent_obj;
QEMUSoundCard card;
@ -73,7 +75,7 @@ typedef struct {
QEMUAudioTimeStamp ats;
FM_OPL *opl;
PortioList port_list;
} AdlibState;
};
static void adlib_stop_opl_timer (AdlibState *s, size_t n)
{

6
hw/audio/cs4231.c
View File

@ -27,6 +27,7 @@
#include "migration/vmstate.h"
#include "qemu/module.h"
#include "trace.h"
#include "qom/object.h"
/*
* In addition to Crystal CS4231 there is a DMA controller on Sparc.
@ -37,17 +38,18 @@
#define CS_MAXDREG (CS_DREGS - 1)
#define TYPE_CS4231 "SUNW,CS4231"
typedef struct CSState CSState;
#define CS4231(obj) \
OBJECT_CHECK(CSState, (obj), TYPE_CS4231)
typedef struct CSState {
struct CSState {
SysBusDevice parent_obj;
MemoryRegion iomem;
qemu_irq irq;
uint32_t regs[CS_REGS];
uint8_t dregs[CS_DREGS];
} CSState;
};
#define CS_RAP(s) ((s)->regs[0] & CS_MAXDREG)
#define CS_VER 0xa0

6
hw/audio/cs4231a.c
View File

@ -32,6 +32,7 @@
#include "qemu/module.h"
#include "qemu/timer.h"
#include "qapi/error.h"
#include "qom/object.h"
/*
Missing features:
@ -62,9 +63,10 @@ static struct {
#define CS_DREGS 32
#define TYPE_CS4231A "cs4231a"
typedef struct CSState CSState;
#define CS4231A(obj) OBJECT_CHECK (CSState, (obj), TYPE_CS4231A)
typedef struct CSState {
struct CSState {
ISADevice dev;
QEMUSoundCard card;
MemoryRegion ioports;
@ -82,7 +84,7 @@ typedef struct CSState {
int aci_counter;
SWVoiceOut *voice;
int16_t *tab;
} CSState;
};
#define MODE2 (1 << 6)
#define MCE (1 << 6)

6
hw/audio/es1370.c
View File

@ -33,6 +33,7 @@
#include "migration/vmstate.h"
#include "qemu/module.h"
#include "sysemu/dma.h"
#include "qom/object.h"
/* Missing stuff:
SCTRL_P[12](END|ST)INC
@ -263,7 +264,7 @@ struct chan {
uint32_t frame_cnt;
};
typedef struct ES1370State {
struct ES1370State {
PCIDevice dev;
QEMUSoundCard card;
MemoryRegion io;
@ -276,7 +277,8 @@ typedef struct ES1370State {
uint32_t mempage;
uint32_t codec;
uint32_t sctl;
} ES1370State;
};
typedef struct ES1370State ES1370State;
struct chan_bits {
uint32_t ctl_en;

6
hw/audio/gus.c
View File

@ -33,6 +33,7 @@
#include "migration/vmstate.h"
#include "gusemu.h"
#include "gustate.h"
#include "qom/object.h"
#define dolog(...) AUD_log ("audio", __VA_ARGS__)
#ifdef DEBUG
@ -42,9 +43,10 @@
#endif
#define TYPE_GUS "gus"
typedef struct GUSState GUSState;
#define GUS(obj) OBJECT_CHECK (GUSState, (obj), TYPE_GUS)
typedef struct GUSState {
struct GUSState {
ISADevice dev;
GUSEmuState emu;
QEMUSoundCard card;
@ -60,7 +62,7 @@ typedef struct GUSState {
IsaDma *isa_dma;
PortioList portio_list1;
PortioList portio_list2;
} GUSState;
};
static uint32_t gus_readb(void *opaque, uint32_t nport)
{

1
hw/audio/hda-codec.c
View File

@ -26,6 +26,7 @@
#include "intel-hda-defs.h"
#include "audio/audio.h"
#include "trace.h"
#include "qom/object.h"
/* -------------------------------------------------------------------------- */

1
hw/audio/intel-hda.c
View File

@ -32,6 +32,7 @@
#include "intel-hda-defs.h"
#include "sysemu/dma.h"
#include "qapi/error.h"
#include "qom/object.h"
/* --------------------------------------------------------------------- */
/* hda bus */

11
hw/audio/intel-hda.h
View File

@ -2,11 +2,14 @@
#define HW_INTEL_HDA_H
#include "hw/qdev-core.h"
#include "qom/object.h"
/* --------------------------------------------------------------------- */
/* hda bus */
#define TYPE_HDA_CODEC_DEVICE "hda-codec"
typedef struct HDACodecDevice HDACodecDevice;
typedef struct HDACodecDeviceClass HDACodecDeviceClass;
#define HDA_CODEC_DEVICE(obj) \
OBJECT_CHECK(HDACodecDevice, (obj), TYPE_HDA_CODEC_DEVICE)
#define HDA_CODEC_DEVICE_CLASS(klass) \
@ -15,10 +18,9 @@
OBJECT_GET_CLASS(HDACodecDeviceClass, (obj), TYPE_HDA_CODEC_DEVICE)
#define TYPE_HDA_BUS "HDA"
typedef struct HDACodecBus HDACodecBus;
#define HDA_BUS(obj) OBJECT_CHECK(HDACodecBus, (obj), TYPE_HDA_BUS)
typedef struct HDACodecBus HDACodecBus;
typedef struct HDACodecDevice HDACodecDevice;
typedef void (*hda_codec_response_func)(HDACodecDevice *dev,
bool solicited, uint32_t response);
@ -33,15 +35,14 @@ struct HDACodecBus {
hda_codec_xfer_func xfer;
};
typedef struct HDACodecDeviceClass
{
struct HDACodecDeviceClass {
DeviceClass parent_class;
int (*init)(HDACodecDevice *dev);
void (*exit)(HDACodecDevice *dev);
void (*command)(HDACodecDevice *dev, uint32_t nid, uint32_t data);
void (*stream)(HDACodecDevice *dev, uint32_t stnr, bool running, bool output);
} HDACodecDeviceClass;
};
struct HDACodecDevice {
DeviceState qdev;

6
hw/audio/marvell_88w8618.c
View File

@ -19,6 +19,7 @@
#include "audio/audio.h"
#include "qapi/error.h"
#include "qemu/module.h"
#include "qom/object.h"
#define MP_AUDIO_SIZE 0x00001000
@ -42,10 +43,11 @@
#define MP_AUDIO_CLOCK_24MHZ (1 << 9)
#define MP_AUDIO_MONO (1 << 14)
typedef struct mv88w8618_audio_state mv88w8618_audio_state;
#define MV88W8618_AUDIO(obj) \
OBJECT_CHECK(mv88w8618_audio_state, (obj), TYPE_MV88W8618_AUDIO)
typedef struct mv88w8618_audio_state {
struct mv88w8618_audio_state {
SysBusDevice parent_obj;
MemoryRegion iomem;
@ -60,7 +62,7 @@ typedef struct mv88w8618_audio_state {
uint32_t last_free;
uint32_t clock_div;
void *wm;
} mv88w8618_audio_state;
};
static void mv88w8618_audio_callback(void *opaque, int free_out, int free_in)
{

3
hw/audio/milkymist-ac97.c
View File

@ -29,6 +29,7 @@
#include "audio/audio.h"
#include "qemu/error-report.h"
#include "qemu/module.h"
#include "qom/object.h"
enum {
R_AC97_CTRL = 0,
@ -55,6 +56,7 @@ enum {
};
#define TYPE_MILKYMIST_AC97 "milkymist-ac97"
typedef struct MilkymistAC97State MilkymistAC97State;
#define MILKYMIST_AC97(obj) \
OBJECT_CHECK(MilkymistAC97State, (obj), TYPE_MILKYMIST_AC97)
@ -74,7 +76,6 @@ struct MilkymistAC97State {
qemu_irq dmar_irq;
qemu_irq dmaw_irq;
};
typedef struct MilkymistAC97State MilkymistAC97State;
static void update_voices(MilkymistAC97State *s)
{

6
hw/audio/pcspk.c
View File

@ -33,15 +33,17 @@
#include "migration/vmstate.h"
#include "hw/audio/pcspk.h"
#include "qapi/error.h"
#include "qom/object.h"
#define PCSPK_BUF_LEN 1792
#define PCSPK_SAMPLE_RATE 32000
#define PCSPK_MAX_FREQ (PCSPK_SAMPLE_RATE >> 1)
#define PCSPK_MIN_COUNT DIV_ROUND_UP(PIT_FREQ, PCSPK_MAX_FREQ)
typedef struct PCSpkState PCSpkState;
#define PC_SPEAKER(obj) OBJECT_CHECK(PCSpkState, (obj), TYPE_PC_SPEAKER)
typedef struct {
struct PCSpkState {
ISADevice parent_obj;
MemoryRegion ioport;
@ -56,7 +58,7 @@ typedef struct {
uint8_t data_on;
uint8_t dummy_refresh_clock;
bool migrate;
} PCSpkState;
};
static const char *s_spk = "pcspk";
static PCSpkState *pcspk_state;

6
hw/audio/pl041.c
View File

@ -30,6 +30,7 @@
#include "pl041.h"
#include "lm4549.h"
#include "migration/vmstate.h"
#include "qom/object.h"
#if 0
#define PL041_DEBUG_LEVEL 1
@ -77,9 +78,10 @@ typedef struct {
} pl041_channel;
#define TYPE_PL041 "pl041"
typedef struct PL041State PL041State;
#define PL041(obj) OBJECT_CHECK(PL041State, (obj), TYPE_PL041)
typedef struct PL041State {
struct PL041State {
SysBusDevice parent_obj;
MemoryRegion iomem;
@ -90,7 +92,7 @@ typedef struct PL041State {
pl041_regfile regs;
pl041_channel fifo1;
lm4549_state codec;
} PL041State;
};
static const unsigned char pl041_default_id[8] = {

6
hw/audio/sb16.c
View File

@ -34,6 +34,7 @@
#include "qemu/log.h"
#include "qemu/module.h"
#include "qapi/error.h"
#include "qom/object.h"
#define dolog(...) AUD_log ("sb16", __VA_ARGS__)
@ -49,9 +50,10 @@
static const char e3[] = "COPYRIGHT (C) CREATIVE TECHNOLOGY LTD, 1992.";
#define TYPE_SB16 "sb16"
typedef struct SB16State SB16State;
#define SB16(obj) OBJECT_CHECK (SB16State, (obj), TYPE_SB16)
typedef struct SB16State {
struct SB16State {
ISADevice parent_obj;
QEMUSoundCard card;
@ -112,7 +114,7 @@ typedef struct SB16State {
int mixer_nreg;
uint8_t mixer_regs[256];
PortioList portio_list;
} SB16State;
};
static void SB_audio_callback (void *opaque, int free);

6
hw/audio/wm8750.c
View File

@ -13,6 +13,7 @@
#include "qemu/module.h"
#include "hw/audio/wm8750.h"
#include "audio/audio.h"
#include "qom/object.h"
#define IN_PORT_N 3
#define OUT_PORT_N 3
@ -26,9 +27,10 @@ typedef struct {
int dac_hz;
} WMRate;
typedef struct WM8750State WM8750State;
#define WM8750(obj) OBJECT_CHECK(WM8750State, (obj), TYPE_WM8750)
typedef struct WM8750State {
struct WM8750State {
I2CSlave parent_obj;
uint8_t i2c_data[2];
@ -54,7 +56,7 @@ typedef struct WM8750State {
const WMRate *rate;
uint8_t rate_vmstate;
int adc_hz, dac_hz, ext_adc_hz, ext_dac_hz, master;
} WM8750State;
};
/* pow(10.0, -i / 20.0) * 255, i = 0..42 */
static const uint8_t wm8750_vol_db_table[] = {

11
hw/avr/arduino.c
View File

@ -15,21 +15,24 @@
#include "hw/boards.h"
#include "atmega.h"
#include "boot.h"
#include "qom/object.h"
typedef struct ArduinoMachineState {
struct ArduinoMachineState {
/*< private >*/
MachineState parent_obj;
/*< public >*/
AtmegaMcuState mcu;
} ArduinoMachineState;
};
typedef struct ArduinoMachineState ArduinoMachineState;
typedef struct ArduinoMachineClass {
struct ArduinoMachineClass {
/*< private >*/
MachineClass parent_class;
/*< public >*/
const char *mcu_type;
uint64_t xtal_hz;
} ArduinoMachineClass;
};
typedef struct ArduinoMachineClass ArduinoMachineClass;
#define TYPE_ARDUINO_MACHINE \
MACHINE_TYPE_NAME("arduino")

6
hw/avr/atmega.c
View File

@ -17,6 +17,7 @@
#include "sysemu/sysemu.h"
#include "hw/qdev-properties.h"
#include "hw/sysbus.h"
#include "qom/object.h"
#include "hw/boards.h" /* FIXME memory_region_allocate_system_memory for sram */
#include "hw/misc/unimp.h"
#include "atmega.h"
@ -45,7 +46,7 @@ typedef struct {
bool is_timer16;
} peripheral_cfg;
typedef struct AtmegaMcuClass {
struct AtmegaMcuClass {
/*< private >*/
SysBusDeviceClass parent_class;
/*< public >*/
@ -59,7 +60,8 @@ typedef struct AtmegaMcuClass {
size_t adc_count;
const uint8_t *irq;
const peripheral_cfg *dev;
} AtmegaMcuClass;
};
typedef struct AtmegaMcuClass AtmegaMcuClass;
#define ATMEGA_MCU_CLASS(klass) \
OBJECT_CLASS_CHECK(AtmegaMcuClass, (klass), TYPE_ATMEGA_MCU)

6
hw/avr/atmega.h
View File

@ -15,6 +15,7 @@
#include "hw/timer/avr_timer16.h"
#include "hw/misc/avr_power.h"
#include "target/avr/cpu.h"
#include "qom/object.h"
#define TYPE_ATMEGA_MCU "ATmega"
#define TYPE_ATMEGA168_MCU "ATmega168"
@ -22,6 +23,7 @@
#define TYPE_ATMEGA1280_MCU "ATmega1280"
#define TYPE_ATMEGA2560_MCU "ATmega2560"
typedef struct AtmegaMcuState AtmegaMcuState;
#define ATMEGA_MCU(obj) OBJECT_CHECK(AtmegaMcuState, (obj), TYPE_ATMEGA_MCU)
#define POWER_MAX 2
@ -29,7 +31,7 @@
#define TIMER_MAX 6
#define GPIO_MAX 12
typedef struct AtmegaMcuState {
struct AtmegaMcuState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
@ -43,6 +45,6 @@ typedef struct AtmegaMcuState {
AVRUsartState usart[USART_MAX];
AVRTimer16State timer[TIMER_MAX];
uint64_t xtal_freq_hz;
} AtmegaMcuState;
};
#endif /* HW_AVR_ATMEGA_H */

21
hw/block/fdc.c
View File

@ -46,6 +46,7 @@
#include "qemu/main-loop.h"
#include "qemu/module.h"
#include "trace.h"
#include "qom/object.h"
/********************************************************/
/* debug Floppy devices */
@ -64,16 +65,17 @@
/* qdev floppy bus */
#define TYPE_FLOPPY_BUS "floppy-bus"
typedef struct FloppyBus FloppyBus;
#define FLOPPY_BUS(obj) OBJECT_CHECK(FloppyBus, (obj), TYPE_FLOPPY_BUS)
typedef struct FDCtrl FDCtrl;
typedef struct FDrive FDrive;
static FDrive *get_drv(FDCtrl *fdctrl, int unit);
typedef struct FloppyBus {
struct FloppyBus {
BusState bus;
FDCtrl *fdc;
} FloppyBus;
};
static const TypeInfo floppy_bus_info = {
.name = TYPE_FLOPPY_BUS,
@ -494,15 +496,16 @@ static const BlockDevOps fd_block_ops = {
#define TYPE_FLOPPY_DRIVE "floppy"
typedef struct FloppyDrive FloppyDrive;
#define FLOPPY_DRIVE(obj) \
OBJECT_CHECK(FloppyDrive, (obj), TYPE_FLOPPY_DRIVE)
typedef struct FloppyDrive {
struct FloppyDrive {
DeviceState qdev;
uint32_t unit;
BlockConf conf;
FloppyDriveType type;
} FloppyDrive;
};
static Property floppy_drive_properties[] = {
DEFINE_PROP_UINT32("unit", FloppyDrive, unit, -1),
@ -886,19 +889,21 @@ static FloppyDriveType get_fallback_drive_type(FDrive *drv)
}
#define TYPE_SYSBUS_FDC "base-sysbus-fdc"
typedef struct FDCtrlSysBus FDCtrlSysBus;
#define SYSBUS_FDC(obj) OBJECT_CHECK(FDCtrlSysBus, (obj), TYPE_SYSBUS_FDC)
typedef struct FDCtrlSysBus {
struct FDCtrlSysBus {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
struct FDCtrl state;
} FDCtrlSysBus;
};
typedef struct FDCtrlISABus FDCtrlISABus;
#define ISA_FDC(obj) OBJECT_CHECK(FDCtrlISABus, (obj), TYPE_ISA_FDC)
typedef struct FDCtrlISABus {
struct FDCtrlISABus {
ISADevice parent_obj;
uint32_t iobase;
@ -907,7 +912,7 @@ typedef struct FDCtrlISABus {
struct FDCtrl state;
int32_t bootindexA;
int32_t bootindexB;
} FDCtrlISABus;
};
static uint32_t fdctrl_read (void *opaque, uint32_t reg)
{

11
hw/block/m25p80.c
View File

@ -33,6 +33,7 @@
#include "qemu/error-report.h"
#include "qapi/error.h"
#include "trace.h"
#include "qom/object.h"
/* Fields for FlashPartInfo->flags */
@ -414,7 +415,7 @@ typedef enum {
#define M25P80_INTERNAL_DATA_BUFFER_SZ 16
typedef struct Flash {
struct Flash {
SSISlave parent_obj;
BlockBackend *blk;
@ -454,12 +455,14 @@ typedef struct Flash {
const FlashPartInfo *pi;
} Flash;
};
typedef struct Flash Flash;
typedef struct M25P80Class {
struct M25P80Class {
SSISlaveClass parent_class;
FlashPartInfo *pi;
} M25P80Class;
};
typedef struct M25P80Class M25P80Class;
#define TYPE_M25P80 "m25p80-generic"
#define M25P80(obj) \

1
hw/block/nand.c
View File

@ -27,6 +27,7 @@
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "qemu/module.h"
#include "qom/object.h"
# define NAND_CMD_READ0 0x00
# define NAND_CMD_READ1 0x01

6
hw/block/onenand.c
View File

@ -31,6 +31,7 @@
#include "qemu/error-report.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "qom/object.h"
/* 11 for 2kB-page OneNAND ("2nd generation") and 10 for 1kB-page chips */
#define PAGE_SHIFT 11
@ -39,9 +40,10 @@
#define BLOCK_SHIFT (PAGE_SHIFT + 6)
#define TYPE_ONE_NAND "onenand"
typedef struct OneNANDState OneNANDState;
#define ONE_NAND(obj) OBJECT_CHECK(OneNANDState, (obj), TYPE_ONE_NAND)
typedef struct OneNANDState {
struct OneNANDState {
SysBusDevice parent_obj;
struct {
@ -85,7 +87,7 @@ typedef struct OneNANDState {
int secs_cur;
int blocks;
uint8_t *blockwp;
} OneNANDState;
};
enum {
ONEN_BUF_BLOCK = 0,

6
hw/char/debugcon.c
View File

@ -30,8 +30,10 @@
#include "chardev/char-fe.h"
#include "hw/isa/isa.h"
#include "hw/qdev-properties.h"
#include "qom/object.h"
#define TYPE_ISA_DEBUGCON_DEVICE "isa-debugcon"
typedef struct ISADebugconState ISADebugconState;
#define ISA_DEBUGCON_DEVICE(obj) \
OBJECT_CHECK(ISADebugconState, (obj), TYPE_ISA_DEBUGCON_DEVICE)
@ -43,12 +45,12 @@ typedef struct DebugconState {
uint32_t readback;
} DebugconState;
typedef struct ISADebugconState {
struct ISADebugconState {
ISADevice parent_obj;
uint32_t iobase;
DebugconState state;
} ISADebugconState;
};
static void debugcon_ioport_write(void *opaque, hwaddr addr, uint64_t val,
unsigned width)

6
hw/char/etraxfs_ser.c
View File

@ -29,6 +29,7 @@
#include "chardev/char-fe.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "qom/object.h"
#define D(x)
@ -49,10 +50,11 @@
#define STAT_TR_RDY 24
#define TYPE_ETRAX_FS_SERIAL "etraxfs,serial"
typedef struct ETRAXSerial ETRAXSerial;
#define ETRAX_SERIAL(obj) \
OBJECT_CHECK(ETRAXSerial, (obj), TYPE_ETRAX_FS_SERIAL)
typedef struct ETRAXSerial {
struct ETRAXSerial {
SysBusDevice parent_obj;
MemoryRegion mmio;
@ -67,7 +69,7 @@ typedef struct ETRAXSerial {
/* Control registers. */
uint32_t regs[R_MAX];
} ETRAXSerial;
};
static void ser_update_irq(ETRAXSerial *s)
{

6
hw/char/exynos4210_uart.c
View File

@ -34,6 +34,7 @@
#include "hw/qdev-properties.h"
#include "trace.h"
#include "qom/object.h"
/*
* Offsets for UART registers relative to SFR base address
@ -138,10 +139,11 @@ typedef struct {
} Exynos4210UartFIFO;
#define TYPE_EXYNOS4210_UART "exynos4210.uart"
typedef struct Exynos4210UartState Exynos4210UartState;
#define EXYNOS4210_UART(obj) \
OBJECT_CHECK(Exynos4210UartState, (obj), TYPE_EXYNOS4210_UART)
typedef struct Exynos4210UartState {
struct Exynos4210UartState {
SysBusDevice parent_obj;
MemoryRegion iomem;
@ -159,7 +161,7 @@ typedef struct Exynos4210UartState {
uint32_t channel;
} Exynos4210UartState;
};
/* Used only for tracing */

6
hw/char/grlib_apbuart.c
View File

@ -31,6 +31,7 @@
#include "chardev/char-fe.h"
#include "trace.h"
#include "qom/object.h"
#define UART_REG_SIZE 20 /* Size of memory mapped registers */
@ -72,10 +73,11 @@
#define FIFO_LENGTH 1024
typedef struct UART UART;
#define GRLIB_APB_UART(obj) \
OBJECT_CHECK(UART, (obj), TYPE_GRLIB_APB_UART)
typedef struct UART {
struct UART {
SysBusDevice parent_obj;
MemoryRegion iomem;
@ -91,7 +93,7 @@ typedef struct UART {
char buffer[FIFO_LENGTH];
int len;
int current;
} UART;
};
static int uart_data_to_read(UART *uart)
{

1
hw/char/ipoctal232.c
View File

@ -16,6 +16,7 @@
#include "qemu/bitops.h"
#include "qemu/module.h"
#include "chardev/char-fe.h"
#include "qom/object.h"
/* #define DEBUG_IPOCTAL */

3
hw/char/lm32_juart.c
View File

@ -26,6 +26,7 @@
#include "hw/char/lm32_juart.h"
#include "hw/qdev-properties.h"
#include "qom/object.h"
enum {
LM32_JUART_MIN_SAVE_VERSION = 0,
@ -41,6 +42,7 @@ enum {
JRX_FULL = (1<<8),
};
typedef struct LM32JuartState LM32JuartState;
#define LM32_JUART(obj) OBJECT_CHECK(LM32JuartState, (obj), TYPE_LM32_JUART)
struct LM32JuartState {
@ -51,7 +53,6 @@ struct LM32JuartState {
uint32_t jtx;
uint32_t jrx;
};
typedef struct LM32JuartState LM32JuartState;
uint32_t lm32_juart_get_jtx(DeviceState *d)
{

3
hw/char/lm32_uart.c
View File

@ -31,6 +31,7 @@
#include "chardev/char-fe.h"
#include "qemu/error-report.h"
#include "qemu/module.h"
#include "qom/object.h"
enum {
R_RXTX = 0,
@ -94,6 +95,7 @@ enum {
};
#define TYPE_LM32_UART "lm32-uart"
typedef struct LM32UartState LM32UartState;
#define LM32_UART(obj) OBJECT_CHECK(LM32UartState, (obj), TYPE_LM32_UART)
struct LM32UartState {
@ -105,7 +107,6 @@ struct LM32UartState {
uint32_t regs[R_MAX];
};
typedef struct LM32UartState LM32UartState;
static void uart_update_irq(LM32UartState *s)
{

6
hw/char/mcf_uart.c
View File

@ -14,8 +14,9 @@
#include "hw/m68k/mcf.h"
#include "hw/qdev-properties.h"
#include "chardev/char-fe.h"
#include "qom/object.h"
typedef struct {
struct mcf_uart_state {
SysBusDevice parent_obj;
MemoryRegion iomem;
@ -33,7 +34,8 @@ typedef struct {
int rx_enabled;
qemu_irq irq;
CharBackend chr;
} mcf_uart_state;
};
typedef struct mcf_uart_state mcf_uart_state;
#define TYPE_MCF_UART "mcf-uart"
#define MCF_UART(obj) OBJECT_CHECK(mcf_uart_state, (obj), TYPE_MCF_UART)

3
hw/char/milkymist-uart.c
View File

@ -30,6 +30,7 @@
#include "chardev/char-fe.h"
#include "qemu/error-report.h"
#include "qemu/module.h"
#include "qom/object.h"
enum {
R_RXTX = 0,
@ -57,6 +58,7 @@ enum {
};
#define TYPE_MILKYMIST_UART "milkymist-uart"
typedef struct MilkymistUartState MilkymistUartState;
#define MILKYMIST_UART(obj) \
OBJECT_CHECK(MilkymistUartState, (obj), TYPE_MILKYMIST_UART)
@ -69,7 +71,6 @@ struct MilkymistUartState {
uint32_t regs[R_MAX];
};
typedef struct MilkymistUartState MilkymistUartState;
static void uart_update_irq(MilkymistUartState *s)
{

6
hw/char/parallel.c
View File

@ -37,6 +37,7 @@
#include "sysemu/reset.h"
#include "sysemu/sysemu.h"
#include "trace.h"
#include "qom/object.h"
//#define DEBUG_PARALLEL
@ -92,17 +93,18 @@ typedef struct ParallelState {
} ParallelState;
#define TYPE_ISA_PARALLEL "isa-parallel"
typedef struct ISAParallelState ISAParallelState;
#define ISA_PARALLEL(obj) \
OBJECT_CHECK(ISAParallelState, (obj), TYPE_ISA_PARALLEL)
typedef struct ISAParallelState {
struct ISAParallelState {
ISADevice parent_obj;
uint32_t index;
uint32_t iobase;
uint32_t isairq;
ParallelState state;
} ISAParallelState;
};
static void parallel_update_irq(ParallelState *s)
{

6
hw/char/sclpconsole-lm.c
View File

@ -24,6 +24,7 @@
#include "hw/s390x/event-facility.h"
#include "hw/qdev-properties.h"
#include "hw/s390x/ebcdic.h"
#include "qom/object.h"
#define SIZE_BUFFER 4096
#define NEWLINE "\n"
@ -37,14 +38,15 @@ typedef struct OprtnsCommand {
/* max size for line-mode data in 4K SCCB page */
#define SIZE_CONSOLE_BUFFER (SCCB_DATA_LEN - sizeof(OprtnsCommand))
typedef struct SCLPConsoleLM {
struct SCLPConsoleLM {
SCLPEvent event;
CharBackend chr;
bool echo; /* immediate echo of input if true */
uint32_t write_errors; /* errors writing to char layer */
uint32_t length; /* length of byte stream in buffer */
uint8_t buf[SIZE_CONSOLE_BUFFER];
} SCLPConsoleLM;
};
typedef struct SCLPConsoleLM SCLPConsoleLM;
#define TYPE_SCLPLM_CONSOLE "sclplmconsole"
#define SCLPLM_CONSOLE(obj) \

6
hw/char/sclpconsole.c
View File

@ -22,6 +22,7 @@
#include "hw/qdev-properties.h"
#include "hw/s390x/event-facility.h"
#include "chardev/char-fe.h"
#include "qom/object.h"
typedef struct ASCIIConsoleData {
EventBufferHeader ebh;
@ -31,7 +32,7 @@ typedef struct ASCIIConsoleData {
/* max size for ASCII data in 4K SCCB page */
#define SIZE_BUFFER_VT220 4080
typedef struct SCLPConsole {
struct SCLPConsole {
SCLPEvent event;
CharBackend chr;
uint8_t iov[SIZE_BUFFER_VT220];
@ -40,7 +41,8 @@ typedef struct SCLPConsole {
uint32_t iov_data_len; /* length of byte stream in buffer */
uint32_t iov_sclp_rest; /* length of byte stream not read via SCLP */
bool notify; /* qemu_notify_event() req'd if true */
} SCLPConsole;
};
typedef struct SCLPConsole SCLPConsole;
#define TYPE_SCLP_CONSOLE "sclpconsole"
#define SCLP_CONSOLE(obj) \

6
hw/char/serial-isa.c
View File

@ -32,17 +32,19 @@
#include "hw/isa/isa.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "qom/object.h"
typedef struct ISASerialState ISASerialState;
#define ISA_SERIAL(obj) OBJECT_CHECK(ISASerialState, (obj), TYPE_ISA_SERIAL)
typedef struct ISASerialState {
struct ISASerialState {
ISADevice parent_obj;
uint32_t index;
uint32_t iobase;
uint32_t isairq;
SerialState state;
} ISASerialState;
};
static const int isa_serial_io[MAX_ISA_SERIAL_PORTS] = {
0x3f8, 0x2f8, 0x3e8, 0x2e8

6
hw/char/serial-pci.c
View File

@ -33,12 +33,14 @@
#include "hw/pci/pci.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "qom/object.h"
typedef struct PCISerialState {
struct PCISerialState {
PCIDevice dev;
SerialState state;
uint8_t prog_if;
} PCISerialState;
};
typedef struct PCISerialState PCISerialState;
#define TYPE_PCI_SERIAL "pci-serial"
#define PCI_SERIAL(s) OBJECT_CHECK(PCISerialState, (s), TYPE_PCI_SERIAL)

6
hw/char/spapr_vty.c
View File

@ -8,15 +8,17 @@
#include "hw/ppc/spapr.h"
#include "hw/ppc/spapr_vio.h"
#include "hw/qdev-properties.h"
#include "qom/object.h"
#define VTERM_BUFSIZE 16
typedef struct SpaprVioVty {
struct SpaprVioVty {
SpaprVioDevice sdev;
CharBackend chardev;
uint32_t in, out;
uint8_t buf[VTERM_BUFSIZE];
} SpaprVioVty;
};
typedef struct SpaprVioVty SpaprVioVty;
#define TYPE_VIO_SPAPR_VTY_DEVICE "spapr-vty"
#define VIO_SPAPR_VTY_DEVICE(obj) \

6
hw/char/terminal3270.c
View File

@ -17,6 +17,7 @@
#include "chardev/char-fe.h"
#include "hw/qdev-properties.h"
#include "hw/s390x/3270-ccw.h"
#include "qom/object.h"
/* Enough spaces for different window sizes. */
#define INPUT_BUFFER_SIZE 1000
@ -26,7 +27,7 @@
*/
#define OUTPUT_BUFFER_SIZE 2051
typedef struct Terminal3270 {
struct Terminal3270 {
EmulatedCcw3270Device cdev;
CharBackend chr;
uint8_t inv[INPUT_BUFFER_SIZE];
@ -34,7 +35,8 @@ typedef struct Terminal3270 {
int in_len;
bool handshake_done;
guint timer_tag;
} Terminal3270;
};
typedef struct Terminal3270 Terminal3270;
#define TYPE_TERMINAL_3270 "x-terminal3270"
#define TERMINAL_3270(obj) \

6
hw/char/virtio-console.c
View File

@ -19,17 +19,19 @@
#include "hw/virtio/virtio-serial.h"
#include "qapi/error.h"
#include "qapi/qapi-events-char.h"
#include "qom/object.h"
#define TYPE_VIRTIO_CONSOLE_SERIAL_PORT "virtserialport"
typedef struct VirtConsole VirtConsole;
#define VIRTIO_CONSOLE(obj) \
OBJECT_CHECK(VirtConsole, (obj), TYPE_VIRTIO_CONSOLE_SERIAL_PORT)
typedef struct VirtConsole {
struct VirtConsole {
VirtIOSerialPort parent_obj;
CharBackend chr;
guint watch;
} VirtConsole;
};
/*
* Callback function that's called from chardevs when backend becomes

6
hw/char/xilinx_uartlite.c
View File

@ -29,6 +29,7 @@
#include "hw/sysbus.h"
#include "qemu/module.h"
#include "chardev/char-fe.h"
#include "qom/object.h"
#define DUART(x)
@ -52,10 +53,11 @@
#define CONTROL_IE 0x10
#define TYPE_XILINX_UARTLITE "xlnx.xps-uartlite"
typedef struct XilinxUARTLite XilinxUARTLite;
#define XILINX_UARTLITE(obj) \
OBJECT_CHECK(XilinxUARTLite, (obj), TYPE_XILINX_UARTLITE)
typedef struct XilinxUARTLite {
struct XilinxUARTLite {
SysBusDevice parent_obj;
MemoryRegion mmio;
@ -67,7 +69,7 @@ typedef struct XilinxUARTLite {
unsigned int rx_fifo_len;
uint32_t regs[R_MAX];
} XilinxUARTLite;
};
static void uart_update_irq(XilinxUARTLite *s)
{

6
hw/cpu/realview_mpcore.c
View File

@ -15,15 +15,17 @@
#include "hw/intc/realview_gic.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "qom/object.h"
#define TYPE_REALVIEW_MPCORE_RIRQ "realview_mpcore"
typedef struct mpcore_rirq_state mpcore_rirq_state;
#define REALVIEW_MPCORE_RIRQ(obj) \
OBJECT_CHECK(mpcore_rirq_state, (obj), TYPE_REALVIEW_MPCORE_RIRQ)
/* Dummy PIC to route IRQ lines. The baseboard has 4 independent IRQ
controllers. The output of these, plus some of the raw input lines
are fed into a single SMP-aware interrupt controller on the CPU. */
typedef struct {
struct mpcore_rirq_state {
SysBusDevice parent_obj;
qemu_irq cpuic[32];
@ -32,7 +34,7 @@ typedef struct {
ARM11MPCorePriveState priv;
RealViewGICState gic[4];
} mpcore_rirq_state;
};
/* Map baseboard IRQs onto CPU IRQ lines. */
static const int mpcore_irq_map[32] = {

6
hw/display/ads7846.c
View File

@ -16,8 +16,9 @@
#include "migration/vmstate.h"
#include "qemu/module.h"
#include "ui/console.h"
#include "qom/object.h"
typedef struct {
struct ADS7846State {
SSISlave ssidev;
qemu_irq interrupt;
@ -27,7 +28,8 @@ typedef struct {
int cycle;
int output;
} ADS7846State;
};
typedef struct ADS7846State ADS7846State;
#define TYPE_ADS7846 "ads7846"
#define ADS7846(obj) OBJECT_CHECK(ADS7846State, (obj), TYPE_ADS7846)

6
hw/display/artist.c
View File

@ -22,8 +22,10 @@
#include "ui/console.h"
#include "trace.h"
#include "framebuffer.h"
#include "qom/object.h"
#define TYPE_ARTIST "artist"
typedef struct ARTISTState ARTISTState;
#define ARTIST(obj) OBJECT_CHECK(ARTISTState, (obj), TYPE_ARTIST)
#ifdef HOST_WORDS_BIGENDIAN
@ -40,7 +42,7 @@ struct vram_buffer {
unsigned int height;
};
typedef struct ARTISTState {
struct ARTISTState {
SysBusDevice parent_obj;
QemuConsole *con;
@ -103,7 +105,7 @@ typedef struct ARTISTState {
uint32_t font_write_pos_y;
int draw_line_pattern;
} ARTISTState;
};
typedef enum {
ARTIST_BUFFER_AP = 1,

6
hw/display/ati_int.h
View File

@ -13,6 +13,7 @@
#include "hw/pci/pci.h"
#include "hw/i2c/bitbang_i2c.h"
#include "vga_int.h"
#include "qom/object.h"
/*#define DEBUG_ATI*/
@ -29,6 +30,7 @@
#define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159
#define TYPE_ATI_VGA "ati-vga"
typedef struct ATIVGAState ATIVGAState;
#define ATI_VGA(obj) OBJECT_CHECK(ATIVGAState, (obj), TYPE_ATI_VGA)
typedef struct ATIVGARegs {
@ -82,7 +84,7 @@ typedef struct ATIVGARegs {
uint32_t default_sc_bottom_right;
} ATIVGARegs;
typedef struct ATIVGAState {
struct ATIVGAState {
PCIDevice dev;
VGACommonState vga;
char *model;
@ -97,7 +99,7 @@ typedef struct ATIVGAState {
MemoryRegion io;
MemoryRegion mm;
ATIVGARegs regs;
} ATIVGAState;
};
const char *ati_reg_name(int num);

6
hw/display/bochs-display.c
View File

@ -18,6 +18,7 @@
#include "ui/console.h"
#include "ui/qemu-pixman.h"
#include "qom/object.h"
typedef struct BochsDisplayMode {
pixman_format_code_t format;
@ -29,7 +30,7 @@ typedef struct BochsDisplayMode {
uint64_t size;
} BochsDisplayMode;
typedef struct BochsDisplayState {
struct BochsDisplayState {
/* parent */
PCIDevice pci;
@ -53,7 +54,8 @@ typedef struct BochsDisplayState {
/* device state */
BochsDisplayMode mode;
} BochsDisplayState;
};
typedef struct BochsDisplayState BochsDisplayState;
#define TYPE_BOCHS_DISPLAY "bochs-display"
#define BOCHS_DISPLAY(obj) OBJECT_CHECK(BochsDisplayState, (obj), \

6
hw/display/cg3.c
View File

@ -36,6 +36,7 @@
#include "qemu/log.h"
#include "qemu/module.h"
#include "trace.h"
#include "qom/object.h"
/* Change to 1 to enable debugging */
#define DEBUG_CG3 0
@ -65,9 +66,10 @@
#define CG3_VRAM_OFFSET 0x800000
#define TYPE_CG3 "cgthree"
typedef struct CG3State CG3State;
#define CG3(obj) OBJECT_CHECK(CG3State, (obj), TYPE_CG3)
typedef struct CG3State {
struct CG3State {
SysBusDevice parent_obj;
QemuConsole *con;
@ -82,7 +84,7 @@ typedef struct CG3State {
uint8_t r[256], g[256], b[256];
uint16_t width, height, depth;
uint8_t dac_index, dac_state;
} CG3State;
};
static void cg3_update_display(void *opaque)
{

6
hw/display/cirrus_vga.c
View File

@ -44,6 +44,7 @@
#include "migration/vmstate.h"
#include "ui/pixel_ops.h"
#include "cirrus_vga_internal.h"
#include "qom/object.h"
/*
* TODO:
@ -178,10 +179,11 @@ typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
uint32_t dstaddr, int dst_pitch,
int width, int height);
typedef struct PCICirrusVGAState {
struct PCICirrusVGAState {
PCIDevice dev;
CirrusVGAState cirrus_vga;
} PCICirrusVGAState;
};
typedef struct PCICirrusVGAState PCICirrusVGAState;
#define TYPE_PCI_CIRRUS_VGA "cirrus-vga"
#define PCI_CIRRUS_VGA(obj) \

6
hw/display/cirrus_vga_isa.c
View File

@ -30,16 +30,18 @@
#include "hw/qdev-properties.h"
#include "hw/isa/isa.h"
#include "cirrus_vga_internal.h"
#include "qom/object.h"
#define TYPE_ISA_CIRRUS_VGA "isa-cirrus-vga"
typedef struct ISACirrusVGAState ISACirrusVGAState;
#define ISA_CIRRUS_VGA(obj) \
OBJECT_CHECK(ISACirrusVGAState, (obj), TYPE_ISA_CIRRUS_VGA)
typedef struct ISACirrusVGAState {
struct ISACirrusVGAState {
ISADevice parent_obj;
CirrusVGAState cirrus_vga;
} ISACirrusVGAState;
};
static void isa_cirrus_vga_realizefn(DeviceState *dev, Error **errp)
{

6
hw/display/exynos4210_fimd.c
View File

@ -32,6 +32,7 @@
#include "qemu/bswap.h"
#include "qemu/module.h"
#include "qemu/log.h"
#include "qom/object.h"
/* Debug messages configuration */
#define EXYNOS4210_FIMD_DEBUG 0
@ -293,10 +294,11 @@ struct Exynos4210fimdWindow {
};
#define TYPE_EXYNOS4210_FIMD "exynos4210.fimd"
typedef struct Exynos4210fimdState Exynos4210fimdState;
#define EXYNOS4210_FIMD(obj) \
OBJECT_CHECK(Exynos4210fimdState, (obj), TYPE_EXYNOS4210_FIMD)
typedef struct {
struct Exynos4210fimdState {
SysBusDevice parent_obj;
MemoryRegion iomem;
@ -325,7 +327,7 @@ typedef struct {
uint8_t *ifb; /* Internal frame buffer */
bool invalidate; /* Image needs to be redrawn */
bool enabled; /* Display controller is enabled */
} Exynos4210fimdState;
};
/* Perform byte/halfword/word swap of data according to WINCON */
static inline void fimd_swap_data(unsigned int swap_ctl, uint64_t *data)

6
hw/display/g364fb.c
View File

@ -29,6 +29,7 @@
#include "trace.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "qom/object.h"
typedef struct G364State {
/* hardware */
@ -486,13 +487,14 @@ static void g364fb_init(DeviceState *dev, G364State *s)
}
#define TYPE_G364 "sysbus-g364"
typedef struct G364SysBusState G364SysBusState;
#define G364(obj) OBJECT_CHECK(G364SysBusState, (obj), TYPE_G364)
typedef struct {
struct G364SysBusState {
SysBusDevice parent_obj;
G364State g364;
} G364SysBusState;
};
static void g364fb_sysbus_realize(DeviceState *dev, Error **errp)
{

6
hw/display/jazz_led.c
View File

@ -29,22 +29,24 @@
#include "trace.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "qom/object.h"
typedef enum {
REDRAW_NONE = 0, REDRAW_SEGMENTS = 1, REDRAW_BACKGROUND = 2,
} screen_state_t;
#define TYPE_JAZZ_LED "jazz-led"
typedef struct LedState LedState;
#define JAZZ_LED(obj) OBJECT_CHECK(LedState, (obj), TYPE_JAZZ_LED)
typedef struct LedState {
struct LedState {
SysBusDevice parent_obj;
MemoryRegion iomem;
uint8_t segments;
QemuConsole *con;
screen_state_t state;
} LedState;
};
static uint64_t jazz_led_read(void *opaque, hwaddr addr,
unsigned int size)

3
hw/display/milkymist-tmu2.c
View File

@ -38,6 +38,7 @@
#include <X11/Xlib.h>
#include <epoxy/gl.h>
#include <epoxy/glx.h>
#include "qom/object.h"
enum {
R_CTL = 0,
@ -82,6 +83,7 @@ struct vertex {
} QEMU_PACKED;
#define TYPE_MILKYMIST_TMU2 "milkymist-tmu2"
typedef struct MilkymistTMU2State MilkymistTMU2State;
#define MILKYMIST_TMU2(obj) \
OBJECT_CHECK(MilkymistTMU2State, (obj), TYPE_MILKYMIST_TMU2)
@ -98,7 +100,6 @@ struct MilkymistTMU2State {
GLXFBConfig glx_fb_config;
GLXContext glx_context;
};
typedef struct MilkymistTMU2State MilkymistTMU2State;
static const int glx_fbconfig_attr[] = {
GLX_GREEN_SIZE, 5,

3
hw/display/milkymist-vgafb.c
View File

@ -32,6 +32,7 @@
#include "ui/pixel_ops.h"
#include "qemu/error-report.h"
#include "qemu/module.h"
#include "qom/object.h"
#define BITS 8
#include "migration/vmstate.h"
@ -68,6 +69,7 @@ enum {
};
#define TYPE_MILKYMIST_VGAFB "milkymist-vgafb"
typedef struct MilkymistVgafbState MilkymistVgafbState;
#define MILKYMIST_VGAFB(obj) \
OBJECT_CHECK(MilkymistVgafbState, (obj), TYPE_MILKYMIST_VGAFB)
@ -84,7 +86,6 @@ struct MilkymistVgafbState {
uint32_t regs[R_MAX];
};
typedef struct MilkymistVgafbState MilkymistVgafbState;
static int vgafb_enabled(MilkymistVgafbState *s)
{

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