s390x/tcg: Implement VECTOR TEST UNDER MASK
Let's return the cc value directly via cpu_env. Unfortunately there isn't a simple way to calculate the value lazily - one would have to calculate and store e.g. the population count of the mask and the result so it can be evaluated in a cc helper. But as VTM only sets the cc, we can assume the value will be needed soon either way. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
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@ -209,6 +209,7 @@ DEF_HELPER_FLAGS_4(gvec_vsra, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
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DEF_HELPER_FLAGS_4(gvec_vsrl, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
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DEF_HELPER_FLAGS_4(gvec_vsrl, TCG_CALL_NO_RWG, void, ptr, cptr, i64, i32)
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DEF_HELPER_FLAGS_4(gvec_vscbi8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_4(gvec_vscbi8, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_4(gvec_vscbi16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
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DEF_HELPER_FLAGS_4(gvec_vscbi16, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
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DEF_HELPER_4(gvec_vtm, void, ptr, cptr, env, i32)
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#ifndef CONFIG_USER_ONLY
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#ifndef CONFIG_USER_ONLY
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DEF_HELPER_3(servc, i32, env, i64, i64)
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DEF_HELPER_3(servc, i32, env, i64, i64)
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@ -1188,6 +1188,8 @@
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F(0xe767, VSUMQ, VRR_c, V, 0, 0, 0, 0, vsumq, 0, IF_VEC)
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F(0xe767, VSUMQ, VRR_c, V, 0, 0, 0, 0, vsumq, 0, IF_VEC)
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/* VECTOR SUM ACROSS WORD */
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/* VECTOR SUM ACROSS WORD */
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F(0xe764, VSUM, VRR_c, V, 0, 0, 0, 0, vsum, 0, IF_VEC)
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F(0xe764, VSUM, VRR_c, V, 0, 0, 0, 0, vsum, 0, IF_VEC)
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/* VECTOR TEST UNDER MASK */
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F(0xe7d8, VTM, VRR_a, V, 0, 0, 0, 0, vtm, 0, IF_VEC)
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#ifndef CONFIG_USER_ONLY
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#ifndef CONFIG_USER_ONLY
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/* COMPARE AND SWAP AND PURGE */
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/* COMPARE AND SWAP AND PURGE */
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@ -191,6 +191,9 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
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#define gen_gvec_2i_ool(v1, v2, c, data, fn) \
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#define gen_gvec_2i_ool(v1, v2, c, data, fn) \
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tcg_gen_gvec_2i_ool(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
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tcg_gen_gvec_2i_ool(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
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c, 16, 16, data, fn)
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c, 16, 16, data, fn)
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#define gen_gvec_2_ptr(v1, v2, ptr, data, fn) \
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tcg_gen_gvec_2_ptr(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
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ptr, 16, 16, data, fn)
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#define gen_gvec_3(v1, v2, v3, gen) \
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#define gen_gvec_3(v1, v2, v3, gen) \
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tcg_gen_gvec_3(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
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tcg_gen_gvec_3(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
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vec_full_reg_offset(v3), 16, 16, gen)
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vec_full_reg_offset(v3), 16, 16, gen)
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@ -2342,3 +2345,11 @@ static DisasJumpType op_vsum(DisasContext *s, DisasOps *o)
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tcg_temp_free_i32(tmp);
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tcg_temp_free_i32(tmp);
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return DISAS_NEXT;
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return DISAS_NEXT;
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}
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}
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static DisasJumpType op_vtm(DisasContext *s, DisasOps *o)
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{
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gen_gvec_2_ptr(get_field(s->fields, v1), get_field(s->fields, v2),
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cpu_env, 0, gen_helper_gvec_vtm);
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set_cc_static(s);
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return DISAS_NEXT;
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}
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@ -28,6 +28,19 @@ static void s390_vec_xor(S390Vector *res, const S390Vector *a,
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res->doubleword[1] = a->doubleword[1] ^ b->doubleword[1];
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res->doubleword[1] = a->doubleword[1] ^ b->doubleword[1];
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}
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}
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static void s390_vec_and(S390Vector *res, const S390Vector *a,
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const S390Vector *b)
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{
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res->doubleword[0] = a->doubleword[0] & b->doubleword[0];
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res->doubleword[1] = a->doubleword[1] & b->doubleword[1];
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}
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static bool s390_vec_equal(const S390Vector *a, const S390Vector *b)
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{
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return a->doubleword[0] == b->doubleword[0] &&
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a->doubleword[1] == b->doubleword[1];
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}
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static void s390_vec_shl(S390Vector *d, const S390Vector *a, uint64_t count)
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static void s390_vec_shl(S390Vector *d, const S390Vector *a, uint64_t count)
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{
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{
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uint64_t tmp;
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uint64_t tmp;
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@ -583,3 +596,21 @@ void HELPER(gvec_vscbi##BITS)(void *v1, const void *v2, const void *v3, \
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}
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}
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DEF_VSCBI(8)
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DEF_VSCBI(8)
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DEF_VSCBI(16)
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DEF_VSCBI(16)
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void HELPER(gvec_vtm)(void *v1, const void *v2, CPUS390XState *env,
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uint32_t desc)
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{
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S390Vector tmp;
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s390_vec_and(&tmp, v1, v2);
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if (s390_vec_is_zero(&tmp)) {
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/* Selected bits all zeros; or all mask bits zero */
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env->cc_op = 0;
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} else if (s390_vec_equal(&tmp, v2)) {
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/* Selected bits all ones */
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env->cc_op = 3;
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} else {
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/* Selected bits a mix of zeros and ones */
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env->cc_op = 1;
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}
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}
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