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tests/avocado: add RISC-V OpenSBI boot test

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This test is used to do a quick sanity check to ensure that we're able
to run the existing QEMU FW image.

'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and
'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN |
RISCV32_BIOS_BIN firmware with minimal options.

The riscv32 'spike' machine isn't bootable at this moment, requiring an
OpenSBI fix [1] and QEMU side changes [2]. We could just leave at that
or add a 'skip' test to remind us about it. To work as a reminder that
we have a riscv32 'spike' test that should be enabled as soon as OpenSBI
QEMU rom receives the fix, we're adding a 'skip' test:

(06/18) tests/avocado/riscv_opensbi.py:RiscvOpenSBI.test_riscv32_spike:
        SKIP: requires OpenSBI fix to work

[1] https://patchwork.ozlabs.org/project/opensbi/patch/20221226033603.1860569-1-bmeng@tinylab.org/
[2] https://patchwork.ozlabs.org/project/qemu-devel/list/?series=334159

Cc: Cleber Rosa <crosa@redhat.com>
Cc: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Tested-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230102115241.25733-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza 2023-01-02 08:52:31 -03:00 committed by Alistair Francis
parent 44e7372b21
commit db2b9a59ca
1 changed files with 65 additions and 0 deletions
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65
tests/avocado/riscv_opensbi.py Normal file
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# OpenSBI boot test for RISC-V machines
#
# Copyright (c) 2022, Ventana Micro
#
# This work is licensed under the terms of the GNU GPL, version 2 or
# later. See the COPYING file in the top-level directory.
from avocado_qemu import QemuSystemTest
from avocado import skip
from avocado_qemu import wait_for_console_pattern
class RiscvOpenSBI(QemuSystemTest):
"""
:avocado: tags=accel:tcg
"""
timeout = 5
def boot_opensbi(self):
self.vm.set_console()
self.vm.launch()
wait_for_console_pattern(self, 'Platform Name')
wait_for_console_pattern(self, 'Boot HART MEDELEG')
@skip("requires OpenSBI fix to work")
def test_riscv32_spike(self):
"""
:avocado: tags=arch:riscv32
:avocado: tags=machine:spike
"""
self.boot_opensbi()
def test_riscv64_spike(self):
"""
:avocado: tags=arch:riscv64
:avocado: tags=machine:spike
"""
self.boot_opensbi()
def test_riscv32_sifive_u(self):
"""
:avocado: tags=arch:riscv32
:avocado: tags=machine:sifive_u
"""
self.boot_opensbi()
def test_riscv64_sifive_u(self):
"""
:avocado: tags=arch:riscv64
:avocado: tags=machine:sifive_u
"""
self.boot_opensbi()
def test_riscv32_virt(self):
"""
:avocado: tags=arch:riscv32
:avocado: tags=machine:virt
"""
self.boot_opensbi()
def test_riscv64_virt(self):
"""
:avocado: tags=arch:riscv64
:avocado: tags=machine:virt
"""
self.boot_opensbi()