stm32f205: Add the stm32f205 SoC
This patch adds the stm32f205 SoC. This will be used by the Netduino 2 to create a machine. Signed-off-by: Alistair Francis <alistair@alistair23.me> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 48d509747a1ea0d8a7d5480560495e679990f9d2.1424175342.git.alistair@alistair23.me Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Alistair Francis
Peter Maydell
parent
bbbbd9002f
commit
db635521a0
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@ -83,6 +83,7 @@ CONFIG_ZYNQ=y
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CONFIG_STM32F2XX_TIMER=y
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CONFIG_STM32F2XX_USART=y
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CONFIG_STM32F2XX_SYSCFG=y
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CONFIG_STM32F205_SOC=y
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CONFIG_VERSATILE_PCI=y
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CONFIG_VERSATILE_I2C=y
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@ -8,3 +8,4 @@ obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
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obj-$(CONFIG_DIGIC) += digic.o
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obj-y += omap1.o omap2.o strongarm.o
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obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
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obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
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@ -0,0 +1,160 @@
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/*
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* STM32F205 SoC
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*
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* Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw/arm/arm.h"
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#include "exec/address-spaces.h"
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#include "hw/arm/stm32f205_soc.h"
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/* At the moment only Timer 2 to 5 are modelled */
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static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400,
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0x40000800, 0x40000C00 };
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static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400,
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0x40004800, 0x40004C00, 0x40005000, 0x40011400 };
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static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50};
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static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71};
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static void stm32f205_soc_initfn(Object *obj)
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{
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STM32F205State *s = STM32F205_SOC(obj);
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int i;
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object_initialize(&s->syscfg, sizeof(s->syscfg), TYPE_STM32F2XX_SYSCFG);
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qdev_set_parent_bus(DEVICE(&s->syscfg), sysbus_get_default());
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for (i = 0; i < STM_NUM_USARTS; i++) {
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object_initialize(&s->usart[i], sizeof(s->usart[i]),
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TYPE_STM32F2XX_USART);
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qdev_set_parent_bus(DEVICE(&s->usart[i]), sysbus_get_default());
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}
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for (i = 0; i < STM_NUM_TIMERS; i++) {
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object_initialize(&s->timer[i], sizeof(s->timer[i]),
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TYPE_STM32F2XX_TIMER);
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qdev_set_parent_bus(DEVICE(&s->timer[i]), sysbus_get_default());
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}
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}
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static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
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{
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STM32F205State *s = STM32F205_SOC(dev_soc);
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DeviceState *syscfgdev, *usartdev, *timerdev;
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SysBusDevice *syscfgbusdev, *usartbusdev, *timerbusdev;
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qemu_irq *pic;
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Error *err = NULL;
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int i;
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MemoryRegion *system_memory = get_system_memory();
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MemoryRegion *sram = g_new(MemoryRegion, 1);
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MemoryRegion *flash = g_new(MemoryRegion, 1);
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MemoryRegion *flash_alias = g_new(MemoryRegion, 1);
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memory_region_init_ram(flash, NULL, "STM32F205.flash", FLASH_SIZE,
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&error_abort);
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memory_region_init_alias(flash_alias, NULL, "STM32F205.flash.alias",
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flash, 0, FLASH_SIZE);
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vmstate_register_ram_global(flash);
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memory_region_set_readonly(flash, true);
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memory_region_set_readonly(flash_alias, true);
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memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash);
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memory_region_add_subregion(system_memory, 0, flash_alias);
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memory_region_init_ram(sram, NULL, "STM32F205.sram", SRAM_SIZE,
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&error_abort);
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vmstate_register_ram_global(sram);
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memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
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pic = armv7m_init(get_system_memory(), FLASH_SIZE, 96,
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s->kernel_filename, s->cpu_model);
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/* System configuration controller */
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syscfgdev = DEVICE(&s->syscfg);
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object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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syscfgbusdev = SYS_BUS_DEVICE(syscfgdev);
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sysbus_mmio_map(syscfgbusdev, 0, 0x40013800);
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sysbus_connect_irq(syscfgbusdev, 0, pic[71]);
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/* Attach UART (uses USART registers) and USART controllers */
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for (i = 0; i < STM_NUM_USARTS; i++) {
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usartdev = DEVICE(&(s->usart[i]));
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object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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usartbusdev = SYS_BUS_DEVICE(usartdev);
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sysbus_mmio_map(usartbusdev, 0, usart_addr[i]);
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sysbus_connect_irq(usartbusdev, 0, pic[usart_irq[i]]);
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}
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/* Timer 2 to 5 */
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for (i = 0; i < STM_NUM_TIMERS; i++) {
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timerdev = DEVICE(&(s->timer[i]));
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qdev_prop_set_uint64(timerdev, "clock-frequency", 1000000000);
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object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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timerbusdev = SYS_BUS_DEVICE(timerdev);
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sysbus_mmio_map(timerbusdev, 0, timer_addr[i]);
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sysbus_connect_irq(timerbusdev, 0, pic[timer_irq[i]]);
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}
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}
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static Property stm32f205_soc_properties[] = {
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DEFINE_PROP_STRING("kernel-filename", STM32F205State, kernel_filename),
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DEFINE_PROP_STRING("cpu-model", STM32F205State, cpu_model),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void stm32f205_soc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = stm32f205_soc_realize;
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dc->props = stm32f205_soc_properties;
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}
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static const TypeInfo stm32f205_soc_info = {
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.name = TYPE_STM32F205_SOC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(STM32F205State),
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.instance_init = stm32f205_soc_initfn,
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.class_init = stm32f205_soc_class_init,
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};
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static void stm32f205_soc_types(void)
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{
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type_register_static(&stm32f205_soc_info);
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}
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type_init(stm32f205_soc_types)
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@ -0,0 +1,57 @@
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/*
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* STM32F205 SoC
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*
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* Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef HW_ARM_STM32F205SOC_H
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#define HW_ARM_STM32F205SOC_H
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#include "hw/misc/stm32f2xx_syscfg.h"
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#include "hw/timer/stm32f2xx_timer.h"
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#include "hw/char/stm32f2xx_usart.h"
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#define TYPE_STM32F205_SOC "stm32f205_soc"
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#define STM32F205_SOC(obj) \
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OBJECT_CHECK(STM32F205State, (obj), TYPE_STM32F205_SOC)
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#define STM_NUM_USARTS 6
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#define STM_NUM_TIMERS 4
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#define FLASH_BASE_ADDRESS 0x08000000
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#define FLASH_SIZE (1024 * 1024)
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#define SRAM_BASE_ADDRESS 0x20000000
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#define SRAM_SIZE (128 * 1024)
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typedef struct STM32F205State {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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char *kernel_filename;
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char *cpu_model;
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STM32F2XXSyscfgState syscfg;
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STM32F2XXUsartState usart[STM_NUM_USARTS];
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STM32F2XXTimerState timer[STM_NUM_TIMERS];
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} STM32F205State;
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#endif
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