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target/riscv: honour show_opcodes when disassembling

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This makes the output suitable when used for plugins.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240305121005.3528075-30-alex.bennee@linaro.org>
This commit is contained in:
Alex Bennée 2024-03-05 12:10:05 +00:00
parent f6e0eabdb4
commit db7e8b1f75
1 changed files with 15 additions and 13 deletions
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28
disas/riscv.c
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@ -5192,19 +5192,21 @@ print_insn_riscv(bfd_vma memaddr, struct disassemble_info *info, rv_isa isa)
} }
} }
switch (len) { if (info->show_opcodes) {
case 2: switch (len) {
(*info->fprintf_func)(info->stream, INST_FMT_2, inst); case 2:
break; (*info->fprintf_func)(info->stream, INST_FMT_2, inst);
case 4: break;
(*info->fprintf_func)(info->stream, INST_FMT_4, inst); case 4:
break; (*info->fprintf_func)(info->stream, INST_FMT_4, inst);
case 6: break;
(*info->fprintf_func)(info->stream, INST_FMT_6, inst); case 6:
break; (*info->fprintf_func)(info->stream, INST_FMT_6, inst);
default: break;
(*info->fprintf_func)(info->stream, INST_FMT_8, inst); default:
break; (*info->fprintf_func)(info->stream, INST_FMT_8, inst);
break;
}
} }
disasm_inst(buf, sizeof(buf), isa, memaddr, inst, disasm_inst(buf, sizeof(buf), isa, memaddr, inst,