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i386: Add get/set/migrate support for SGX_LEPUBKEYHASH MSRs

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On real hardware, on systems that supports SGX Launch Control, those
MSRs are initialized to digest of Intel's signing key; on systems that
don't support SGX Launch Control, those MSRs are not available but
hardware always uses digest of Intel's signing key in EINIT.

KVM advertises SGX LC via CPUID if and only if the MSRs are writable.
Unconditionally initialize those MSRs to digest of Intel's signing key
when CPU is realized and reset to reflect the fact. This avoids
potential bug in case kvm_arch_put_registers() is called before
kvm_arch_get_registers() is called, in which case guest's virtual
SGX_LEPUBKEYHASH MSRs will be set to 0, although KVM initializes those
to digest of Intel's signing key by default, since KVM allows those MSRs
to be updated by Qemu to support live migration.

Save/restore the SGX Launch Enclave Public Key Hash MSRs if SGX Launch
Control (LC) is exposed to the guest. Likewise, migrate the MSRs if they
are writable by the guest.

Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Kai Huang <kai.huang@intel.com>
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20210719112136.57018-11-yang.zhong@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Sean Christopherson 2021-07-19 19:21:13 +08:00 committed by Paolo Bonzini
parent 165981a5e6
commit db88806523
4 changed files with 58 additions and 1 deletions
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16
target/i386/cpu.c
View File

@ -5700,6 +5700,17 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
}
}
static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env)
{
#ifndef CONFIG_USER_ONLY
/* Those default values are defined in Skylake HW */
env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL;
env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL;
env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL;
env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL;
#endif
}
static void x86_cpu_reset(DeviceState *dev)
{
CPUState *s = CPU(dev);
@ -5832,6 +5843,8 @@ static void x86_cpu_reset(DeviceState *dev)
if (kvm_enabled()) {
kvm_arch_reset_vcpu(cpu);
}
x86_cpu_set_sgxlepubkeyhash(env);
#endif
}
@ -6214,6 +6227,8 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
& CPUID_EXT2_AMD_ALIASES);
}
x86_cpu_set_sgxlepubkeyhash(env);
/*
* note: the call to the framework needs to happen after feature expansion,
* but before the checks/modifications to ucode_rev, mwait, phys_bits.
@ -6901,7 +6916,6 @@ static const TypeInfo x86_cpu_type_info = {
.class_init = x86_cpu_common_class_init,
};
/* "base" CPU model, used by query-cpu-model-expansion */
static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
{

1
target/i386/cpu.h
View File

@ -1516,6 +1516,7 @@ typedef struct CPUX86State {
uint64_t mcg_status;
uint64_t msr_ia32_misc_enable;
uint64_t msr_ia32_feature_control;
uint64_t msr_ia32_sgxlepubkeyhash[4];
uint64_t msr_fixed_ctr_ctrl;
uint64_t msr_global_ctrl;

22
target/i386/kvm/kvm.c
View File

@ -3107,6 +3107,17 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
}
}
if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_SGX_LC) {
kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH0,
env->msr_ia32_sgxlepubkeyhash[0]);
kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH1,
env->msr_ia32_sgxlepubkeyhash[1]);
kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH2,
env->msr_ia32_sgxlepubkeyhash[2]);
kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH3,
env->msr_ia32_sgxlepubkeyhash[3]);
}
/* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
* kvm_put_msr_feature_control. */
}
@ -3446,6 +3457,13 @@ static int kvm_get_msrs(X86CPU *cpu)
}
}
if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_SGX_LC) {
kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH0, 0);
kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH1, 0);
kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH2, 0);
kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH3, 0);
}
ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
if (ret < 0) {
return ret;
@ -3735,6 +3753,10 @@ static int kvm_get_msrs(X86CPU *cpu)
case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
break;
case MSR_IA32_SGXLEPUBKEYHASH0 ... MSR_IA32_SGXLEPUBKEYHASH3:
env->msr_ia32_sgxlepubkeyhash[index - MSR_IA32_SGXLEPUBKEYHASH0] =
msrs[i].data;
break;
}
}

20
target/i386/machine.c
View File

@ -1415,6 +1415,25 @@ static const VMStateDescription vmstate_msr_tsx_ctrl = {
}
};
static bool intel_sgx_msrs_needed(void *opaque)
{
X86CPU *cpu = opaque;
CPUX86State *env = &cpu->env;
return !!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_SGX_LC);
}
static const VMStateDescription vmstate_msr_intel_sgx = {
.name = "cpu/intel_sgx",
.version_id = 1,
.minimum_version_id = 1,
.needed = intel_sgx_msrs_needed,
.fields = (VMStateField[]) {
VMSTATE_UINT64_ARRAY(env.msr_ia32_sgxlepubkeyhash, X86CPU, 4),
VMSTATE_END_OF_LIST()
}
};
const VMStateDescription vmstate_x86_cpu = {
.name = "cpu",
.version_id = 12,
@ -1551,6 +1570,7 @@ const VMStateDescription vmstate_x86_cpu = {
&vmstate_nested_state,
#endif
&vmstate_msr_tsx_ctrl,
&vmstate_msr_intel_sgx,
NULL
}
};