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target/openrisc: Populate CPUClass.mmu_index 

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2024-01-29 10:13:23 +10:00
parent 498c7d78d3
commit db8b41941a
2 changed files with 15 additions and 8 deletions
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13
target/openrisc/cpu.c
View File

@ -68,6 +68,18 @@ static bool openrisc_cpu_has_work(CPUState *cs)
CPU_INTERRUPT_TIMER); CPU_INTERRUPT_TIMER);
} }
int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch)
{
CPUOpenRISCState *env = cpu_env(cs);
if (env->sr & (ifetch ? SR_IME : SR_DME)) {
/* The mmu is enabled; test supervisor state. */
return env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX;
}
return MMU_NOMMU_IDX; /* mmu is disabled */
}
static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info) static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info)
{ {
info->print_insn = print_insn_or1k; info->print_insn = print_insn_or1k;
@ -239,6 +251,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = openrisc_cpu_class_by_name; cc->class_by_name = openrisc_cpu_class_by_name;
cc->has_work = openrisc_cpu_has_work; cc->has_work = openrisc_cpu_has_work;
cc->mmu_index = openrisc_cpu_mmu_index;
cc->dump_state = openrisc_cpu_dump_state; cc->dump_state = openrisc_cpu_dump_state;
cc->set_pc = openrisc_cpu_set_pc; cc->set_pc = openrisc_cpu_set_pc;
cc->get_pc = openrisc_cpu_get_pc; cc->get_pc = openrisc_cpu_get_pc;

10
target/openrisc/cpu.h
View File

@ -361,16 +361,10 @@ static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, vaddr *pc,
| (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE));
} }
int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch);
static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch) static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch)
{ {
int ret = MMU_NOMMU_IDX; /* mmu is disabled */ return openrisc_cpu_mmu_index(env_cpu(env), ifetch);
if (env->sr & (ifetch ? SR_IME : SR_DME)) {
/* The mmu is enabled; test supervisor state. */
ret = env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX;
}
return ret;
} }
static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env) static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env)