ssi: cache SSIPeripheralClass to avoid GET_CLASS()
Investigating why some BMC models are so slow compared to a plain ARM virt machines I did some profiling of: ./qemu-system-arm -M romulus-bmc -nic user \ -drive file=obmc-phosphor-image-romulus.static.mtd,format=raw,if=mtd \ -nographic -serial mon:stdio And saw that object_class_dynamic_cast_assert was dominating the profile times. We have a number of cases in this model of the SSI bus. As the class is static once the object is created we just cache it and use it instead of the dynamic case macros. Profiling against: ./tests/venv/bin/avocado run \ tests/avocado/machine_aspeed.py:test_arm_ast2500_romulus_openbmc_v2_9_0 Before: 35.565 s ± 0.087 s After: 15.713 s ± 0.287 s Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Cc: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220811151413.3350684-6-alex.bennee@linaro.org> Message-Id: <20220923084803.498337-6-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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hw/ssi/ssi.c
18
hw/ssi/ssi.c
@ -38,9 +38,8 @@ static void ssi_cs_default(void *opaque, int n, int level)
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bool cs = !!level;
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assert(n == 0);
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if (s->cs != cs) {
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SSIPeripheralClass *ssc = SSI_PERIPHERAL_GET_CLASS(s);
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if (ssc->set_cs) {
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ssc->set_cs(s, cs);
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if (s->spc->set_cs) {
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s->spc->set_cs(s, cs);
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}
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}
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s->cs = cs;
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@ -48,11 +47,11 @@ static void ssi_cs_default(void *opaque, int n, int level)
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static uint32_t ssi_transfer_raw_default(SSIPeripheral *dev, uint32_t val)
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{
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SSIPeripheralClass *ssc = SSI_PERIPHERAL_GET_CLASS(dev);
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SSIPeripheralClass *ssc = dev->spc;
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if ((dev->cs && ssc->cs_polarity == SSI_CS_HIGH) ||
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(!dev->cs && ssc->cs_polarity == SSI_CS_LOW) ||
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ssc->cs_polarity == SSI_CS_NONE) {
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(!dev->cs && ssc->cs_polarity == SSI_CS_LOW) ||
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ssc->cs_polarity == SSI_CS_NONE) {
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return ssc->transfer(dev, val);
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}
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return 0;
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@ -67,6 +66,7 @@ static void ssi_peripheral_realize(DeviceState *dev, Error **errp)
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ssc->cs_polarity != SSI_CS_NONE) {
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qdev_init_gpio_in_named(dev, ssi_cs_default, SSI_GPIO_CS, 1);
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}
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s->spc = ssc;
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ssc->realize(s, errp);
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}
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@ -115,13 +115,11 @@ uint32_t ssi_transfer(SSIBus *bus, uint32_t val)
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{
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BusState *b = BUS(bus);
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BusChild *kid;
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SSIPeripheralClass *ssc;
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uint32_t r = 0;
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QTAILQ_FOREACH(kid, &b->children, sibling) {
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SSIPeripheral *peripheral = SSI_PERIPHERAL(kid->child);
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ssc = SSI_PERIPHERAL_GET_CLASS(peripheral);
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r |= ssc->transfer_raw(peripheral, val);
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SSIPeripheral *p = SSI_PERIPHERAL(kid->child);
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r |= p->spc->transfer_raw(p, val);
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}
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return r;
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@ -59,6 +59,9 @@ struct SSIPeripheralClass {
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struct SSIPeripheral {
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DeviceState parent_obj;
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/* cache the class */
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SSIPeripheralClass *spc;
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/* Chip select state */
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bool cs;
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};
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