e2k: very basic SIC emulation
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285
hw/e2k/sic.c
285
hw/e2k/sic.c
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@ -1,6 +1,8 @@
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/*
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* Copyright (c) 2021 Alibek Omarov
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*
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* System Interchange Controller emulation
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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@ -12,7 +14,7 @@
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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*/
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#include "qemu/osdep.h"
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#include "qemu/datadir.h"
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#include "qemu/log.h"
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@ -30,79 +32,258 @@
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#define ES2_NSR_AREA_PHYS_BASE 0x0000000110000000UL /* node 0 */
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#define ES2_NBSR_AREA_SIZE 0x0000000000100000UL
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enum SICRegsAddrs
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{
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SIC_node_offset = 0x4,
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SIC_st_p = 0x0,
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SIC_rt_lcfg0 = 0x10, /* node configuration, max nodes 4 */
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SIC_rt_mhi0 = 0x20,
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SIC_rt_mlo0 = 0x30,
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SIC_rt_pcim0 = 0x40,
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SIC_rt_pciio0 = 0x50,
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SIC_rt_ioapic0 = 0x60,
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SIC_rt_pcicfgb = 0x90,
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SIC_st_core = 0x100, /* core configuration, max cores 16 */
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/* IO link & RDMA */
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SIC_iol_csr = 0x900,
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SIC_unknown_0x1040 = 0x1040,
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SIC_unknown_0x1050 = 0x1050,
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SIC_rt_ioapic10 = 0x1060,
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/* Second IO link */
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SIC_iol_csr1 = 0x1900,
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};
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#define SIC_rt_msi 0xb0
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#define SIC_rt_msi_h 0xb4
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#define SIC_rt_pcim0 0x40
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#define SIC_rt_pcim1 0x44
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#define SIC_rt_pcim2 0x48
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#define SIC_rt_pcim3 0x4c
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#define SIC_rt_pciio0 0x50
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#define SIC_rt_pciio1 0x54
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#define SIC_rt_pciio2 0x58
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#define SIC_rt_pciio3 0x5c
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#define SIC_rt_pcimp_b0 0x70
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#define SIC_rt_pcimp_b1 0x74
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#define SIC_rt_pcimp_b2 0x78
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#define SIC_rt_pcimp_b3 0x7c
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#define SIC_rt_pcimp_e0 0x80
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#define SIC_rt_pcimp_e1 0x84
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#define SIC_rt_pcimp_e2 0x88
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#define SIC_rt_pcimp_e3 0x8c
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#define SIC_rt_pcicfgb 0x90
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#define SIC_prepic_ctrl2 0x8030
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#define SIC_prepic_err_stat 0x8040
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#define SIC_prepic_err_int 0x8060
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#define SIC_prepic_linp0 0x8c00
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#define SIC_prepic_linp1 0x8c04
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#define SIC_prepic_linp2 0x8c08
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#define SIC_prepic_linp3 0x8c0c
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#define SIC_prepic_linp4 0x8c10
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#define SIC_prepic_linp5 0x8c14
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#define SIC_iommu_ctrl 0x0380
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#define SIC_iommu_ba_lo 0x0390
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#define SIC_iommu_dtba_lo 0x0398
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#define SIC_iommu_err 0x03b0
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#define SIC_iommu_err_info_lo 0x03b8
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static uint64_t sic_mem_read(void *opaque, hwaddr addr, unsigned size)
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{
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// E2KMachineState *ms = opaque;
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uint64_t val;
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E2KMachineState *ms = opaque;
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SICState *regs = &ms->sicregs;
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uint64_t ret;
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int index;
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if (size < 4) {
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return 0;
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}
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index = addr & (ES2_NBSR_AREA_SIZE - 1);
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switch (index) {
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case SIC_rt_msi:
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ret = regs->rt_msi & 0xffffffff;
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break;
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case SIC_rt_msi_h:
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ret = regs->rt_msi >> 32;
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break;
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case SIC_rt_pcim0:
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val = 0;
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ret = regs->rt_pcim0;
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break;
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case SIC_rt_pcim1:
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ret = regs->rt_pcim1;
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break;
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case SIC_rt_pcim2:
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ret = regs->rt_pcim2;
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break;
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case SIC_rt_pcim3:
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ret = regs->rt_pcim3;
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break;
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case SIC_rt_pciio0:
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val = 0;
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ret = regs->rt_pciio0;
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break;
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case SIC_rt_pciio1:
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ret = regs->rt_pciio1;
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break;
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case SIC_rt_pciio2:
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ret = regs->rt_pciio2;
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break;
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case SIC_rt_pciio3:
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ret = regs->rt_pciio3;
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break;
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case SIC_rt_pcimp_b0:
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ret = regs->rt_pcimp_b0;
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break;
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case SIC_rt_pcimp_b1:
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ret = regs->rt_pcimp_b1;
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break;
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case SIC_rt_pcimp_b2:
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ret = regs->rt_pcimp_b2;
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break;
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case SIC_rt_pcimp_b3:
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ret = regs->rt_pcimp_b3;
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break;
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case SIC_rt_pcimp_e0:
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ret = regs->rt_pcimp_e0;
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break;
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case SIC_rt_pcimp_e1:
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ret = regs->rt_pcimp_e1;
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break;
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case SIC_rt_pcimp_e2:
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ret = regs->rt_pcimp_e2;
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break;
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case SIC_rt_pcimp_e3:
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ret = regs->rt_pcimp_e3;
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break;
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case SIC_rt_pcicfgb:
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// TODO: io page address [48:12]
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// TODO: page + 0x8044 = 16-bit reg
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val = 0xdeadbeef000 >> 12;
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ret = regs->rt_pcicfgb;
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break;
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case SIC_prepic_ctrl2:
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ret = regs->prepic_ctrl2;
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break;
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case SIC_prepic_err_stat:
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ret = regs->prepic_err_stat;
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break;
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case SIC_prepic_err_int:
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ret = regs->prepic_err_int;
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break;
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case SIC_prepic_linp0:
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ret = regs->prepic_linp0;
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break;
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case SIC_prepic_linp1:
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ret = regs->prepic_linp1;
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break;
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case SIC_prepic_linp2:
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ret = regs->prepic_linp2;
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break;
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case SIC_prepic_linp3:
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ret = regs->prepic_linp3;
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break;
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case SIC_prepic_linp4:
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ret = regs->prepic_linp4;
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break;
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case SIC_prepic_linp5:
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ret = regs->prepic_linp5;
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break;
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case SIC_iommu_err:
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ret = regs->iommu_err;
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break;
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case SIC_iommu_err_info_lo:
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ret = regs->iommu_err_info;
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break;
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default:
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val = 0;
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qemu_log_mask(LOG_UNIMP, "%s: unknown SIC register 0x%x\n", __FUNCTION__, index);
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ret = 0;
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break;
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}
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trace_sic_mem_readl(addr, val);
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return val;
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trace_sic_mem_readl(addr, ret);
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return ret;
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}
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static void sic_mem_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned size)
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{
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// E2KMachineState *ms = opaque;
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E2KMachineState *ms = opaque;
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SICState *regs = &ms->sicregs;
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int index;
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trace_sic_mem_writel(addr, val);
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index = addr & (ES2_NBSR_AREA_SIZE - 1);
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switch (index) {
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case SIC_rt_msi:
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regs->rt_msi = (regs->rt_msi & 0xffffffff00000000) | val;
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break;
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case SIC_rt_msi_h:
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regs->rt_msi = (regs->rt_msi & 0x00000000ffffffff) | (val << 32);
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break;
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case SIC_rt_pcim0:
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regs->rt_pcim0 = val;
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break;
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case SIC_rt_pcim1:
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regs->rt_pcim1 = val;
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break;
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case SIC_rt_pcim2:
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regs->rt_pcim2 = val;
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break;
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case SIC_rt_pcim3:
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regs->rt_pcim3 = val;
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break;
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case SIC_rt_pciio0:
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regs->rt_pciio0 = val;
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break;
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case SIC_rt_pciio1:
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regs->rt_pciio1 = val;
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break;
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case SIC_rt_pciio2:
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regs->rt_pciio2 = val;
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break;
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case SIC_rt_pciio3:
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regs->rt_pciio3 = val;
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break;
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case SIC_rt_pcimp_b0:
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regs->rt_pcimp_b0 = val;
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break;
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case SIC_rt_pcimp_b1:
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regs->rt_pcimp_b1 = val;
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break;
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case SIC_rt_pcimp_b2:
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regs->rt_pcimp_b2 = val;
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break;
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case SIC_rt_pcimp_b3:
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regs->rt_pcimp_b3 = val;
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break;
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case SIC_rt_pcimp_e0:
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regs->rt_pcimp_e0 = val;
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break;
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case SIC_rt_pcimp_e1:
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regs->rt_pcimp_e1 = val;
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break;
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case SIC_rt_pcimp_e2:
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regs->rt_pcimp_e2 = val;
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break;
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case SIC_rt_pcimp_e3:
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regs->rt_pcimp_e3 = val;
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break;
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case SIC_rt_pcicfgb:
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regs->rt_pcicfgb = val;
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break;
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case SIC_prepic_ctrl2:
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regs->prepic_ctrl2 = val;
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break;
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case SIC_prepic_err_stat:
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regs->prepic_err_stat = val;
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break;
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case SIC_prepic_err_int:
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regs->prepic_err_int = val;
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break;
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case SIC_prepic_linp0:
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regs->prepic_linp0 = val;
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break;
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case SIC_prepic_linp1:
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regs->prepic_linp1 = val;
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break;
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case SIC_prepic_linp2:
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regs->prepic_linp2 = val;
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break;
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case SIC_prepic_linp3:
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regs->prepic_linp3 = val;
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break;
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case SIC_prepic_linp4:
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regs->prepic_linp4 = val;
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break;
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case SIC_prepic_linp5:
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regs->prepic_linp5 = val;
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break;
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case SIC_iommu_ctrl:
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regs->iommu_ctrl = val;
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break;
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case SIC_iommu_ba_lo:
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regs->iommu_ptbar = val;
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break;
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case SIC_iommu_dtba_lo:
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regs->iommu_dtbar = val;
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "%s: unknown SIC register 0x%x\n", __FUNCTION__, index);
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break;
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}
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trace_sic_mem_writel(addr, val);
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}
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static const MemoryRegionOps sic_io_ops = {
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@ -121,6 +302,8 @@ void sic_init(E2KMachineState *ms)
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const hwaddr base = ES2_NSR_AREA_PHYS_BASE;
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const uint64_t size = ES2_NBSR_AREA_SIZE;
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memset(&ms->sicregs, 0, sizeof(ms->sicregs));
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io_memory = g_malloc(sizeof(*io_memory));
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memory_region_init_io(io_memory, OBJECT(ms), &sic_io_ops, ms, "sic-msi",
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size);
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@ -23,6 +23,41 @@
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#include "qom/object.h"
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#include "hw/e2k/ioapic.h"
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typedef struct SICState {
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uint32_t rt_pcim0;
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uint32_t rt_pcim1;
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uint32_t rt_pcim2;
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uint32_t rt_pcim3;
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uint32_t rt_pciio0;
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uint32_t rt_pciio1;
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uint32_t rt_pciio2;
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uint32_t rt_pciio3;
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uint32_t rt_pcimp_b0;
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uint32_t rt_pcimp_b1;
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uint32_t rt_pcimp_b2;
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uint32_t rt_pcimp_b3;
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uint32_t rt_pcimp_e0;
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uint32_t rt_pcimp_e1;
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uint32_t rt_pcimp_e2;
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uint32_t rt_pcimp_e3;
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uint32_t rt_pcicfgb;
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uint64_t rt_msi;
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uint32_t iommu_ctrl;
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uint64_t iommu_ptbar;
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uint64_t iommu_dtbar;
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uint64_t iommu_err;
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uint64_t iommu_err_info;
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uint32_t prepic_ctrl2;
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uint32_t prepic_err_stat;
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uint32_t prepic_err_int;
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uint32_t prepic_linp0;
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uint32_t prepic_linp1;
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uint32_t prepic_linp2;
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uint32_t prepic_linp3;
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uint32_t prepic_linp4;
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uint32_t prepic_linp5;
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} SICState;
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struct E2KMachineClass {
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/*< private >*/
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MachineClass parent;
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@ -36,6 +71,10 @@ struct E2KMachineState {
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/*< public >*/
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qemu_irq *pic;
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struct SICState sicregs;
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AddressSpace *ioapic_as;
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};
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#define TYPE_E2K_MACHINE MACHINE_TYPE_NAME("e2k")
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