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target/arm: Add is_secure parameter to v8m_security_lookup 

Remove the use of regime_is_secure from v8m_security_lookup,
passing the new parameter to the lookup instead.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220822152741.1617527-12-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2022-08-22 08:26:46 -07:00 committed by Peter Maydell
parent 652c750ee5
commit dbf2a71ad6
3 changed files with 12 additions and 8 deletions
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2
target/arm/internals.h
View File

@ -1123,7 +1123,7 @@ typedef struct V8M_SAttributes {
void v8m_security_lookup(CPUARMState *env, uint32_t address,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
V8M_SAttributes *sattrs);
bool secure, V8M_SAttributes *sattrs);
/* Cacheability and shareability attributes for a memory access */
typedef struct ARMCacheAttrs {

9
target/arm/m_helper.c
View File

@ -689,7 +689,8 @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure,
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
V8M_SAttributes sattrs = {};
v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, &sattrs);
v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx,
targets_secure, &sattrs);
if (sattrs.ns) {
attrs.secure = false;
} else if (!targets_secure) {
@ -2002,7 +2003,8 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
ARMMMUFaultInfo fi = {};
MemTxResult txres;
v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, &sattrs);
v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx,
regime_is_secure(env, mmu_idx), &sattrs);
if (!sattrs.nsc || sattrs.ns) {
/*
* This must be the second half of the insn, and it straddles a
@ -2826,7 +2828,8 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
}
if (env->v7m.secure) {
v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, &sattrs);
v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx,
targetsec, &sattrs);
nsr = sattrs.ns && r;
nsrw = sattrs.ns && rw;
} else {

9
target/arm/ptw.c
View File

@ -1857,8 +1857,8 @@ static bool v8m_is_sau_exempt(CPUARMState *env,
}
void v8m_security_lookup(CPUARMState *env, uint32_t address,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
V8M_SAttributes *sattrs)
MMUAccessType access_type, ARMMMUIdx mmu_idx,
bool is_secure, V8M_SAttributes *sattrs)
{
/*
* Look up the security attributes for this address. Compare the
@ -1886,7 +1886,7 @@ void v8m_security_lookup(CPUARMState *env, uint32_t address,
}
if (idau_exempt || v8m_is_sau_exempt(env, address, access_type)) {
sattrs->ns = !regime_is_secure(env, mmu_idx);
sattrs->ns = !is_secure;
return;
}
@ -1975,7 +1975,8 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
bool ret;
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
v8m_security_lookup(env, address, access_type, mmu_idx, &sattrs);
v8m_security_lookup(env, address, access_type, mmu_idx,
secure, &sattrs);
if (access_type == MMU_INST_FETCH) {
/*
* Instruction fetches always use the MMU bank and the