OpenE2K/qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

target/arm: Clear exclusive monitor on v7M reset, exception entry/exit

Browse Source 
For M profile we must clear the exclusive monitor on reset, exception
entry and exception exit.  We weren't doing any of these things; fix
this bug.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1505137930-13255-3-git-send-email-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2017-09-14 18:43:16 +01:00
parent 4a16724f06
commit dc3c4c14f0
4 changed files with 19 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
target/arm/cpu.c
View File

@ -235,6 +235,12 @@ static void arm_cpu_reset(CPUState *s)
env->regs[15] = 0xFFFF0000;
}
/* M profile requires that reset clears the exclusive monitor;
* A profile does not, but clearing it makes more sense than having it
* set with an exclusive access on address zero.
*/
arm_clear_exclusive(env);
env->vfp.xregs[ARM_VFP_FPEXC] = 0;
#endif

2
target/arm/helper.c
View File

@ -6175,6 +6175,7 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr)
armv7m_nvic_acknowledge_irq(env->nvic);
switch_v7m_sp(env, 0);
arm_clear_exclusive(env);
/* Clear IT bits */
env->condexec_bits = 0;
env->regs[14] = lr;
@ -6354,6 +6355,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu)
}
/* Otherwise, we have a successful exception exit. */
arm_clear_exclusive(env);
qemu_log_mask(CPU_LOG_INT, "...successful exception return\n");
}

10
target/arm/internals.h
View File

@ -443,6 +443,16 @@ bool arm_is_psci_call(ARMCPU *cpu, int excp_type);
void arm_handle_psci_call(ARMCPU *cpu);
#endif
/**
* arm_clear_exclusive: clear the exclusive monitor
* @env: CPU env
* Clear the CPU's exclusive monitor, like the guest CLREX instruction.
*/
static inline void arm_clear_exclusive(CPUARMState *env)
{
env->exclusive_addr = -1;
}
/**
* ARMMMUFaultInfo: Information describing an ARM MMU Fault
* @s2addr: Address that caused a fault at stage 2

2
target/arm/op_helper.c
View File

@ -1022,7 +1022,7 @@ void HELPER(exception_return)(CPUARMState *env)
aarch64_save_sp(env, cur_el);
env->exclusive_addr = -1;
arm_clear_exclusive(env);
/* We must squash the PSTATE.SS bit to zero unless both of the
* following hold: