tcg-sparc: Implement ANDC.
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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@ -224,6 +224,7 @@ static inline int tcg_target_const_match(tcg_target_long val,
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#define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00))
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#define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10))
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#define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01))
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#define ARITH_ANDN (INSN_OP(2) | INSN_OP3(0x05))
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#define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02))
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#define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12))
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#define ARITH_ORN (INSN_OP(2) | INSN_OP3(0x06))
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@ -1216,6 +1217,9 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
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OP_32_64(and):
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c = ARITH_AND;
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goto gen_arith;
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OP_32_64(andc):
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c = ARITH_ANDN;
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goto gen_arith;
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OP_32_64(or):
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c = ARITH_OR;
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goto gen_arith;
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@ -1436,6 +1440,7 @@ static const TCGTargetOpDef sparc_op_defs[] = {
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{ INDEX_op_remu_i32, { "r", "r", "rJ" } },
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{ INDEX_op_sub_i32, { "r", "r", "rJ" } },
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{ INDEX_op_and_i32, { "r", "r", "rJ" } },
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{ INDEX_op_andc_i32, { "r", "r", "rJ" } },
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{ INDEX_op_or_i32, { "r", "r", "rJ" } },
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{ INDEX_op_xor_i32, { "r", "r", "rJ" } },
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@ -1493,6 +1498,7 @@ static const TCGTargetOpDef sparc_op_defs[] = {
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{ INDEX_op_remu_i64, { "r", "r", "rJ" } },
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{ INDEX_op_sub_i64, { "r", "r", "rJ" } },
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{ INDEX_op_and_i64, { "r", "r", "rJ" } },
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{ INDEX_op_andc_i64, { "r", "r", "rJ" } },
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{ INDEX_op_or_i64, { "r", "r", "rJ" } },
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{ INDEX_op_xor_i64, { "r", "r", "rJ" } },
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@ -93,12 +93,14 @@ enum {
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#define TCG_TARGET_HAS_neg_i32
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#define TCG_TARGET_HAS_not_i32
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#define TCG_TARGET_HAS_andc_i32
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#if TCG_TARGET_REG_BITS == 64
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#define TCG_TARGET_HAS_ext32s_i64
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#define TCG_TARGET_HAS_ext32u_i64
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#define TCG_TARGET_HAS_neg_i64
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#define TCG_TARGET_HAS_not_i64
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#define TCG_TARGET_HAS_andc_i64
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#endif
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//#define TCG_TARGET_HAS_bswap32_i32
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