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target-arm: Fix implementation of TLB invalidate operations

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Fix some bugs in the implementation of the TLB invalidate
operations on ARM:
 * the 'invalidate all' op was not passing flush_global=1
   to tlb_flush(); this doesn't have a practical effect since
   tlb_flush() currently ignores that argument, but is
   semantically incorrect
 * 'invalidate by address for all ASIDs' was implemented as
   flushing the whole TLB, which invalidates much more than
   strictly necessary. Use tlb_flush_page() instead.
We also annotate the ops with the ARM ARM official acronyms.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2012-01-25 11:49:46 +00:00
parent 5b4448d27d
commit dc8714ca57
1 changed files with 6 additions and 7 deletions
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13
target-arm/helper.c
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@ -1610,18 +1610,17 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
break;
case 8: /* MMU TLB control. */
switch (op2) {
case 0: /* Invalidate all. */
tlb_flush(env, 0);
case 0: /* Invalidate all (TLBIALL) */
tlb_flush(env, 1);
break;
case 1: /* Invalidate single TLB entry. */
case 1: /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
tlb_flush_page(env, val & TARGET_PAGE_MASK);
break;
case 2: /* Invalidate on ASID. */
case 2: /* Invalidate by ASID (TLBIASID) */
tlb_flush(env, val == 0);
break;
case 3: /* Invalidate single entry on MVA. */
/* ??? This is like case 1, but ignores ASID. */
tlb_flush(env, 1);
case 3: /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
tlb_flush_page(env, val & TARGET_PAGE_MASK);
break;
default:
goto bad_reg;