ppc-40x: Correct ESR for zone protection faults.
Raise the zone protection fault in ESR for TLB faults caused by zone protection bits. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
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@ -1171,6 +1171,8 @@ static int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
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break;
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case 0x0:
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if (pr != 0) {
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/* Raise Zone protection fault. */
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env->spr[SPR_40x_ESR] = 1 << 22;
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ctx->prot = 0;
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ret = -2;
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break;
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@ -1183,6 +1185,8 @@ static int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
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ctx->prot = tlb->prot;
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ctx->prot |= PAGE_EXEC;
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ret = check_prot(ctx->prot, rw, access_type);
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if (ret == -2)
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env->spr[SPR_40x_ESR] = 0;
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break;
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}
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if (ret >= 0) {
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@ -1580,11 +1584,20 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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/* Access rights violation */
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env->exception_index = POWERPC_EXCP_DSI;
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env->error_code = 0;
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env->spr[SPR_DAR] = address;
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if (rw == 1)
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env->spr[SPR_DSISR] = 0x0A000000;
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else
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env->spr[SPR_DSISR] = 0x08000000;
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if (env->mmu_model == POWERPC_MMU_SOFT_4xx
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|| env->mmu_model == POWERPC_MMU_SOFT_4xx_Z) {
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env->spr[SPR_40x_DEAR] = address;
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if (rw) {
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env->spr[SPR_40x_ESR] |= 0x00800000;
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}
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} else {
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env->spr[SPR_DAR] = address;
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if (rw == 1) {
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env->spr[SPR_DSISR] = 0x0A000000;
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} else {
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env->spr[SPR_DSISR] = 0x08000000;
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}
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}
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break;
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case -4:
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/* Direct store exception */
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