tcg/tci: Remove tci_read_r32s
Use explicit casts for ext32s opcodes. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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984ae87314
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tcg/tci.c
20
tcg/tci.c
@ -57,13 +57,6 @@ static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg index)
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return regs[index];
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return regs[index];
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}
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}
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#if TCG_TARGET_REG_BITS == 64
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static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index)
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{
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return (int32_t)tci_read_reg(regs, index);
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}
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#endif
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#if TCG_TARGET_REG_BITS == 64
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#if TCG_TARGET_REG_BITS == 64
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static uint64_t tci_read_reg64(const tcg_target_ulong *regs, TCGReg index)
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static uint64_t tci_read_reg64(const tcg_target_ulong *regs, TCGReg index)
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{
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{
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@ -149,15 +142,6 @@ static uint64_t tci_read_r64(const tcg_target_ulong *regs,
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return tci_uint64(tci_read_r(regs, tb_ptr), low);
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return tci_uint64(tci_read_r(regs, tb_ptr), low);
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}
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}
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#elif TCG_TARGET_REG_BITS == 64
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#elif TCG_TARGET_REG_BITS == 64
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/* Read indexed register (32 bit signed) from bytecode. */
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static int32_t tci_read_r32s(const tcg_target_ulong *regs,
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const uint8_t **tb_ptr)
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{
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int32_t value = tci_read_reg32s(regs, **tb_ptr);
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*tb_ptr += 1;
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return value;
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}
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/* Read indexed register (64 bit) from bytecode. */
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/* Read indexed register (64 bit) from bytecode. */
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static uint64_t tci_read_r64(const tcg_target_ulong *regs,
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static uint64_t tci_read_r64(const tcg_target_ulong *regs,
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const uint8_t **tb_ptr)
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const uint8_t **tb_ptr)
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@ -870,8 +854,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
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#endif
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#endif
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case INDEX_op_ext_i32_i64:
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case INDEX_op_ext_i32_i64:
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t0 = *tb_ptr++;
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t0 = *tb_ptr++;
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t1 = tci_read_r32s(regs, &tb_ptr);
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t1 = tci_read_r(regs, &tb_ptr);
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tci_write_reg(regs, t0, t1);
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tci_write_reg(regs, t0, (int32_t)t1);
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break;
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break;
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#if TCG_TARGET_HAS_ext32u_i64
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#if TCG_TARGET_HAS_ext32u_i64
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case INDEX_op_ext32u_i64:
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case INDEX_op_ext32u_i64:
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