target/riscv: remove RISCV_FEATURE_MMU
RISCV_FEATURE_MMU is set whether cpu->cfg.mmu is set, so let's just use the flag directly instead. With this change the enum is also removed. It is worth noticing that this enum, and all the RISCV_FEATURES_* that were contained in it, predates the existence of the cpu->cfg object. Today, using cpu->cfg is an easier way to retrieve all the features and extensions enabled in the hart. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230222185205.355361-10-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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@ -919,10 +919,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
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}
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}
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if (cpu->cfg.mmu) {
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riscv_set_feature(env, RISCV_FEATURE_MMU);
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}
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if (cpu->cfg.epmp && !cpu->cfg.pmp) {
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/*
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* Enhanced PMP should only be available
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@ -81,13 +81,6 @@
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#define RVH RV('H')
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#define RVJ RV('J')
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/* S extension denotes that Supervisor mode exists, however it is possible
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to have a core that support S mode but does not have an MMU and there
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is currently no bit in misa to indicate whether an MMU exists or not
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so a cpu features bitfield is required, likewise for optional PMP support */
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enum {
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RISCV_FEATURE_MMU,
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};
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/* Privileged specification version */
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enum {
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@ -796,7 +796,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
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mode = PRV_U;
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}
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if (mode == PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) {
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if (mode == PRV_M || !riscv_cpu_cfg(env)->mmu) {
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*physical = addr;
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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return TRANSLATE_SUCCESS;
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@ -2621,7 +2621,7 @@ static RISCVException rmw_siph(CPURISCVState *env, int csrno,
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static RISCVException read_satp(CPURISCVState *env, int csrno,
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target_ulong *val)
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{
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if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
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if (!riscv_cpu_cfg(env)->mmu) {
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*val = 0;
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return RISCV_EXCP_NONE;
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}
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@ -2640,7 +2640,7 @@ static RISCVException write_satp(CPURISCVState *env, int csrno,
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{
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target_ulong vm, mask;
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if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
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if (!riscv_cpu_cfg(env)->mmu) {
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return RISCV_EXCP_NONE;
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}
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@ -218,7 +218,7 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict)
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return;
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}
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if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
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if (!riscv_cpu_cfg(env)->mmu) {
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monitor_printf(mon, "S-mode MMU unavailable\n");
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return;
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}
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@ -315,7 +315,7 @@ int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
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}
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if (size == 0) {
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if (riscv_feature(env, RISCV_FEATURE_MMU)) {
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if (riscv_cpu_cfg(env)->mmu) {
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/*
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* If size is unknown (0), assume that all bytes
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* from addr to the end of the page will be accessed.
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