OpenE2K
/
qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

Add missing file. Fix spelling errors. 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4800 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
pbrook 2008-06-29 10:43:16 +00:00
parent 2e70f6efa8
commit dd5d6fe913
4 changed files with 58 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

56
gen-icount.h Normal file
View File

@ -0,0 +1,56 @@
/* Helpewrs for instruction counting code genration. */
static TCGArg *icount_arg;
static int icount_label;
static inline void gen_icount_start(void)
{
TCGv count;
if (!use_icount)
return;
icount_label = gen_new_label();
/* FIXME: This generates lousy code. We can't use tcg_new_temp because
count needs to live over the conditional branch. To workaround this
we allow the target to supply a convenient register temporary. */
#ifndef ICOUNT_TEMP
count = tcg_temp_local_new(TCG_TYPE_I32);
#else
count = ICOUNT_TEMP;
#endif
tcg_gen_ld_i32(count, cpu_env, offsetof(CPUState, icount_decr.u32));
/* This is a horrid hack to allow fixing up the value later. */
icount_arg = gen_opparam_ptr + 1;
tcg_gen_subi_i32(count, count, 0xdeadbeef);
tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, icount_label);
tcg_gen_st16_i32(count, cpu_env, offsetof(CPUState, icount_decr.u16.low));
#ifndef ICOUNT_TEMP
tcg_temp_free(count);
#endif
}
static void gen_icount_end(TranslationBlock *tb, int num_insns)
{
if (use_icount) {
*icount_arg = num_insns;
gen_set_label(icount_label);
tcg_gen_exit_tb((long)tb + 2);
}
}
static void inline gen_io_start(void)
{
TCGv tmp = tcg_const_i32(1);
tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, can_do_io));
tcg_temp_free(tmp);
}
static inline void gen_io_end(void)
{
TCGv tmp = tcg_const_i32(0);
tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, can_do_io));
tcg_temp_free(tmp);
}

2
qemu-doc.texi
View File

@ -974,7 +974,7 @@ time within a few seconds of real time.
Note that while this option can give deterministic behavior, it does not
provide cycle accurate emulation. Modern CPUs contain superscalar out of
order cores with complex cache heirachies. The number of instructions
order cores with complex cache hierarchies. The number of instructions
executed often has little or no correlation with actual performance.
@end table

1
target-mips/translate.c
View File

@ -7861,7 +7861,6 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
#else
ctx.mem_idx = ctx.hflags & MIPS_HFLAG_KSU;
#endif
num_insns = 0;
num_insns = 0;
max_insns = tb->cflags & CF_COUNT_MASK;
if (max_insns == 0)

2
vl.c
View File

@ -7446,7 +7446,7 @@ static void help(int exitcode)
" To see what timers are available use -clock ?\n"
"-startdate select initial date of the clock\n"
"-icount [N|auto]\n"
" Enable virtual instruction counter with 2^N clock ticks per instructon\n"
" Enable virtual instruction counter with 2^N clock ticks per instruction\n"
"\n"
"During emulation, the following keys are useful:\n"
"ctrl-alt-f toggle full screen\n"