target/ppc: Optimize x[sv]xsigdp using deposit_i64()
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20190309214255.9952-3-f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -1587,8 +1587,7 @@ static void gen_xsxsigdp(DisasContext *ctx)
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tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
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tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
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get_cpu_vsrh(t1, xB(ctx->opcode));
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tcg_gen_andi_i64(rt, t1, 0x000FFFFFFFFFFFFF);
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tcg_gen_or_i64(rt, rt, t0);
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tcg_gen_deposit_i64(rt, t0, t1, 0, 52);
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tcg_temp_free_i64(t0);
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tcg_temp_free_i64(t1);
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@ -1624,8 +1623,7 @@ static void gen_xsxsigqp(DisasContext *ctx)
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tcg_gen_movi_i64(t0, 0x0001000000000000);
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tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
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tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
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tcg_gen_andi_i64(xth, xbh, 0x0000FFFFFFFFFFFF);
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tcg_gen_or_i64(xth, xth, t0);
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tcg_gen_deposit_i64(xth, t0, xbh, 0, 48);
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set_cpu_vsrh(rD(ctx->opcode) + 32, xth);
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tcg_gen_mov_i64(xtl, xbl);
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set_cpu_vsrl(rD(ctx->opcode) + 32, xtl);
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@ -1814,16 +1812,14 @@ static void gen_xvxsigdp(DisasContext *ctx)
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tcg_gen_movi_i64(t0, 0x0010000000000000);
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tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
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tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
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tcg_gen_andi_i64(xth, xbh, 0x000FFFFFFFFFFFFF);
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tcg_gen_or_i64(xth, xth, t0);
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tcg_gen_deposit_i64(xth, t0, xbh, 0, 52);
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set_cpu_vsrh(xT(ctx->opcode), xth);
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tcg_gen_extract_i64(exp, xbl, 52, 11);
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tcg_gen_movi_i64(t0, 0x0010000000000000);
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tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
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tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
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tcg_gen_andi_i64(xtl, xbl, 0x000FFFFFFFFFFFFF);
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tcg_gen_or_i64(xtl, xtl, t0);
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tcg_gen_deposit_i64(xth, t0, xbl, 0, 52);
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set_cpu_vsrl(xT(ctx->opcode), xtl);
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tcg_temp_free_i64(t0);
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