target/arm: Unindent unnecessary else-clause
Now that the if() branch of the condition in aarch64_max_initfn() returns early, we don't need to keep the rest of the code in the function inside an else block. Remove the else, unindenting that code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Alexander Graf <agraf@csgraf.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220204165506.2846058-5-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell
parent
0baa21be49
commit
ddaebdda53
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@ -707,176 +707,179 @@ static void aarch64_host_initfn(Object *obj)
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static void aarch64_max_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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uint64_t t;
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uint32_t u;
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if (kvm_enabled()) {
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/* With KVM, '-cpu max' is identical to '-cpu host' */
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aarch64_host_initfn(obj);
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return;
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} else {
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uint64_t t;
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uint32_t u;
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aarch64_a57_initfn(obj);
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}
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/*
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* Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real
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* one and try to apply errata workarounds or use impdef features we
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* don't provide.
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* An IMPLEMENTER field of 0 means "reserved for software use";
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* ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers
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* to see which features are present";
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* the VARIANT, PARTNUM and REVISION fields are all implementation
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* defined and we choose to define PARTNUM just in case guest
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* code needs to distinguish this QEMU CPU from other software
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* implementations, though this shouldn't be needed.
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*/
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t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0);
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t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf);
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t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q');
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t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0);
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t = FIELD_DP64(t, MIDR_EL1, REVISION, 0);
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cpu->midr = t;
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/* '-cpu max' for TCG: we currently do this as "A57 with extra things" */
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t = cpu->isar.id_aa64isar0;
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t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */
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t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);
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t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */
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t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
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t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);
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t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);
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t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);
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t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);
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t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
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t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
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t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
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t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */
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t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */
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t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);
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cpu->isar.id_aa64isar0 = t;
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aarch64_a57_initfn(obj);
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t = cpu->isar.id_aa64isar1;
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t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2);
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t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);
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t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);
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t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
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t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
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t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1);
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t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);
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t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */
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t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1);
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cpu->isar.id_aa64isar1 = t;
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/*
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* Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real
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* one and try to apply errata workarounds or use impdef features we
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* don't provide.
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* An IMPLEMENTER field of 0 means "reserved for software use";
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* ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers
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* to see which features are present";
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* the VARIANT, PARTNUM and REVISION fields are all implementation
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* defined and we choose to define PARTNUM just in case guest
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* code needs to distinguish this QEMU CPU from other software
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* implementations, though this shouldn't be needed.
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*/
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t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0);
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t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf);
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t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q');
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t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0);
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t = FIELD_DP64(t, MIDR_EL1, REVISION, 0);
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cpu->midr = t;
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t = cpu->isar.id_aa64pfr0;
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t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
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t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);
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t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
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t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);
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t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);
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cpu->isar.id_aa64pfr0 = t;
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t = cpu->isar.id_aa64isar0;
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t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */
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t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);
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t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */
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t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
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t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);
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t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);
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t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);
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t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);
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t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
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t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
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t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
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t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */
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t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */
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t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);
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cpu->isar.id_aa64isar0 = t;
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t = cpu->isar.id_aa64pfr1;
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t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
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t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2);
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/*
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* Begin with full support for MTE. This will be downgraded to MTE=0
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* during realize if the board provides no tag memory, much like
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* we do for EL2 with the virtualization=on property.
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*/
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t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);
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cpu->isar.id_aa64pfr1 = t;
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t = cpu->isar.id_aa64isar1;
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t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2);
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t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);
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t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);
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t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
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t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
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t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1);
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t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);
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t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */
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t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1);
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cpu->isar.id_aa64isar1 = t;
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t = cpu->isar.id_aa64mmfr0;
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t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 5); /* PARange: 48 bits */
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cpu->isar.id_aa64mmfr0 = t;
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t = cpu->isar.id_aa64pfr0;
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t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
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t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);
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t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
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t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);
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t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);
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cpu->isar.id_aa64pfr0 = t;
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t = cpu->isar.id_aa64mmfr1;
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t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
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t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
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t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);
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t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */
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t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */
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t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */
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cpu->isar.id_aa64mmfr1 = t;
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t = cpu->isar.id_aa64pfr1;
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t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
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t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2);
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/*
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* Begin with full support for MTE. This will be downgraded to MTE=0
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* during realize if the board provides no tag memory, much like
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* we do for EL2 with the virtualization=on property.
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*/
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t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);
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cpu->isar.id_aa64pfr1 = t;
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t = cpu->isar.id_aa64mmfr2;
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t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);
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t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
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t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
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cpu->isar.id_aa64mmfr2 = t;
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t = cpu->isar.id_aa64mmfr0;
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t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 5); /* PARange: 48 bits */
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cpu->isar.id_aa64mmfr0 = t;
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t = cpu->isar.id_aa64zfr0;
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t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
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t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* PMULL */
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t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1);
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t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1);
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t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1);
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t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1);
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t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1);
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t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1);
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t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);
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cpu->isar.id_aa64zfr0 = t;
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t = cpu->isar.id_aa64mmfr1;
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t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
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t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
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t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);
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t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */
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t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */
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t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */
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cpu->isar.id_aa64mmfr1 = t;
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/* Replicate the same data to the 32-bit id registers. */
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u = cpu->isar.id_isar5;
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u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */
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u = FIELD_DP32(u, ID_ISAR5, SHA1, 1);
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u = FIELD_DP32(u, ID_ISAR5, SHA2, 1);
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u = FIELD_DP32(u, ID_ISAR5, CRC32, 1);
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u = FIELD_DP32(u, ID_ISAR5, RDM, 1);
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u = FIELD_DP32(u, ID_ISAR5, VCMA, 1);
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cpu->isar.id_isar5 = u;
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t = cpu->isar.id_aa64mmfr2;
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t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);
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t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
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t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
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cpu->isar.id_aa64mmfr2 = t;
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u = cpu->isar.id_isar6;
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u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
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u = FIELD_DP32(u, ID_ISAR6, DP, 1);
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u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
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u = FIELD_DP32(u, ID_ISAR6, SB, 1);
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u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
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u = FIELD_DP32(u, ID_ISAR6, BF16, 1);
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u = FIELD_DP32(u, ID_ISAR6, I8MM, 1);
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cpu->isar.id_isar6 = u;
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t = cpu->isar.id_aa64zfr0;
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t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
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t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* PMULL */
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t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1);
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t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1);
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t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1);
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t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1);
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t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1);
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t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1);
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t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);
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cpu->isar.id_aa64zfr0 = t;
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u = cpu->isar.id_pfr0;
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u = FIELD_DP32(u, ID_PFR0, DIT, 1);
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cpu->isar.id_pfr0 = u;
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/* Replicate the same data to the 32-bit id registers. */
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u = cpu->isar.id_isar5;
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u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */
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u = FIELD_DP32(u, ID_ISAR5, SHA1, 1);
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u = FIELD_DP32(u, ID_ISAR5, SHA2, 1);
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u = FIELD_DP32(u, ID_ISAR5, CRC32, 1);
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u = FIELD_DP32(u, ID_ISAR5, RDM, 1);
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u = FIELD_DP32(u, ID_ISAR5, VCMA, 1);
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cpu->isar.id_isar5 = u;
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u = cpu->isar.id_pfr2;
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u = FIELD_DP32(u, ID_PFR2, SSBS, 1);
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cpu->isar.id_pfr2 = u;
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u = cpu->isar.id_isar6;
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u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
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u = FIELD_DP32(u, ID_ISAR6, DP, 1);
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u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
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u = FIELD_DP32(u, ID_ISAR6, SB, 1);
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u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
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u = FIELD_DP32(u, ID_ISAR6, BF16, 1);
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u = FIELD_DP32(u, ID_ISAR6, I8MM, 1);
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cpu->isar.id_isar6 = u;
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u = cpu->isar.id_mmfr3;
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u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
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cpu->isar.id_mmfr3 = u;
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u = cpu->isar.id_pfr0;
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u = FIELD_DP32(u, ID_PFR0, DIT, 1);
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cpu->isar.id_pfr0 = u;
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u = cpu->isar.id_mmfr4;
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u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */
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u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
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u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */
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u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */
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cpu->isar.id_mmfr4 = u;
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u = cpu->isar.id_pfr2;
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u = FIELD_DP32(u, ID_PFR2, SSBS, 1);
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cpu->isar.id_pfr2 = u;
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t = cpu->isar.id_aa64dfr0;
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t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
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cpu->isar.id_aa64dfr0 = t;
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u = cpu->isar.id_mmfr3;
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u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
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cpu->isar.id_mmfr3 = u;
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u = cpu->isar.id_dfr0;
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u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
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cpu->isar.id_dfr0 = u;
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u = cpu->isar.id_mmfr4;
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u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */
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u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
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u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */
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u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */
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cpu->isar.id_mmfr4 = u;
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u = cpu->isar.mvfr1;
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u = FIELD_DP32(u, MVFR1, FPHP, 3); /* v8.2-FP16 */
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u = FIELD_DP32(u, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
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cpu->isar.mvfr1 = u;
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t = cpu->isar.id_aa64dfr0;
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t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
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cpu->isar.id_aa64dfr0 = t;
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u = cpu->isar.id_dfr0;
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u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
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cpu->isar.id_dfr0 = u;
|
||||
|
||||
u = cpu->isar.mvfr1;
|
||||
u = FIELD_DP32(u, MVFR1, FPHP, 3); /* v8.2-FP16 */
|
||||
u = FIELD_DP32(u, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
|
||||
cpu->isar.mvfr1 = u;
|
||||
|
||||
#ifdef CONFIG_USER_ONLY
|
||||
/* For usermode -cpu max we can use a larger and more efficient DCZ
|
||||
* blocksize since we don't have to follow what the hardware does.
|
||||
*/
|
||||
cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
|
||||
cpu->dcz_blocksize = 7; /* 512 bytes */
|
||||
/*
|
||||
* For usermode -cpu max we can use a larger and more efficient DCZ
|
||||
* blocksize since we don't have to follow what the hardware does.
|
||||
*/
|
||||
cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
|
||||
cpu->dcz_blocksize = 7; /* 512 bytes */
|
||||
#endif
|
||||
|
||||
bitmap_fill(cpu->sve_vq_supported, ARM_MAX_VQ);
|
||||
}
|
||||
bitmap_fill(cpu->sve_vq_supported, ARM_MAX_VQ);
|
||||
|
||||
aarch64_add_pauth_properties(obj);
|
||||
aarch64_add_sve_properties(obj);
|
||||
|
|
|
|||
Loading…
Reference in New Issue