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target-mips: do not allow Status.FR=0 mode in 64-bit FPU 

Status.FR bit must be ignored on write and read as 1 when an implementation of
Release 6 of the Architecture in which a 64-bit floating point unit is
implemented.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
This commit is contained in:
Leon Alrae 2014-06-27 08:49:07 +01:00
parent 3f4938833c
commit ddc584bdb5
1 changed files with 6 additions and 0 deletions
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6
target-mips/translate.c
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@ -17951,6 +17951,12 @@ void cpu_state_reset(CPUMIPSState *env)
}
}
#endif
if ((env->insn_flags & ISA_MIPS32R6) &&
(env->active_fpu.fcr0 & (1 << FCR0_F64))) {
/* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */
env->CP0_Status |= (1 << CP0St_FR);
}
compute_hflags(env);
cs->exception_index = EXCP_NONE;
}