misc: Add a pca9554 GPIO device model
Specs are available here:
https://www.nxp.com/docs/en/data-sheet/PCA9554_9554A.pdf
This is a simple model supporting the basic registers for GPIO
mode. The device also supports an interrupt output line but the
model does not yet support this.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
Glenn Miles
Nicholas Piggin
parent
7b85f008b6
commit
de0c7d543b
10
MAINTAINERS
10
MAINTAINERS
@ -1170,9 +1170,7 @@ R: Joel Stanley <joel@jms.id.au>
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L: qemu-arm@nongnu.org
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S: Maintained
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F: hw/*/*aspeed*
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F: hw/misc/pca9552.c
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F: include/hw/*/*aspeed*
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F: include/hw/misc/pca9552*.h
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F: hw/net/ftgmac100.c
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F: include/hw/net/ftgmac100.h
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F: docs/system/arm/aspeed.rst
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@ -1544,6 +1542,14 @@ F: include/hw/pci-host/pnv*
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F: pc-bios/skiboot.lid
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F: tests/qtest/pnv*
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pca955x
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M: Glenn Miles <milesg@linux.vnet.ibm.com>
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L: qemu-ppc@nongnu.org
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L: qemu-arm@nongnu.org
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S: Odd Fixes
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F: hw/misc/pca955*.c
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F: include/hw/misc/pca955*.h
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virtex_ml507
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M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
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L: qemu-ppc@nongnu.org
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328
hw/misc/pca9554.c
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328
hw/misc/pca9554.c
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@ -0,0 +1,328 @@
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/*
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* PCA9554 I/O port
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*
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* Copyright (c) 2023, IBM Corporation.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "qemu/bitops.h"
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#include "hw/qdev-properties.h"
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#include "hw/misc/pca9554.h"
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#include "hw/misc/pca9554_regs.h"
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#include "hw/irq.h"
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#include "migration/vmstate.h"
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#include "qapi/error.h"
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#include "qapi/visitor.h"
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#include "trace.h"
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#include "qom/object.h"
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struct PCA9554Class {
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/*< private >*/
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I2CSlaveClass parent_class;
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/*< public >*/
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};
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typedef struct PCA9554Class PCA9554Class;
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DECLARE_CLASS_CHECKERS(PCA9554Class, PCA9554,
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TYPE_PCA9554)
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#define PCA9554_PIN_LOW 0x0
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#define PCA9554_PIN_HIZ 0x1
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static const char *pin_state[] = {"low", "high"};
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static void pca9554_update_pin_input(PCA9554State *s)
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{
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int i;
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uint8_t config = s->regs[PCA9554_CONFIG];
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uint8_t output = s->regs[PCA9554_OUTPUT];
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uint8_t internal_state = config | output;
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for (i = 0; i < PCA9554_PIN_COUNT; i++) {
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uint8_t bit_mask = 1 << i;
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uint8_t internal_pin_state = (internal_state >> i) & 0x1;
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uint8_t old_value = s->regs[PCA9554_INPUT] & bit_mask;
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uint8_t new_value;
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switch (internal_pin_state) {
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case PCA9554_PIN_LOW:
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s->regs[PCA9554_INPUT] &= ~bit_mask;
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break;
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case PCA9554_PIN_HIZ:
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/*
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* pullup sets it to a logical 1 unless
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* external device drives it low.
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*/
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if (s->ext_state[i] == PCA9554_PIN_LOW) {
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s->regs[PCA9554_INPUT] &= ~bit_mask;
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} else {
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s->regs[PCA9554_INPUT] |= bit_mask;
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}
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break;
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default:
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break;
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}
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/* update irq state only if pin state changed */
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new_value = s->regs[PCA9554_INPUT] & bit_mask;
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if (new_value != old_value) {
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if (new_value) {
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/* changed from 0 to 1 */
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qemu_set_irq(s->gpio_out[i], 1);
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} else {
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/* changed from 1 to 0 */
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qemu_set_irq(s->gpio_out[i], 0);
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}
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}
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}
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}
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static uint8_t pca9554_read(PCA9554State *s, uint8_t reg)
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{
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switch (reg) {
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case PCA9554_INPUT:
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return s->regs[PCA9554_INPUT] ^ s->regs[PCA9554_POLARITY];
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case PCA9554_OUTPUT:
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case PCA9554_POLARITY:
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case PCA9554_CONFIG:
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return s->regs[reg];
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: unexpected read to register %d\n",
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__func__, reg);
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return 0xFF;
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}
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}
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static void pca9554_write(PCA9554State *s, uint8_t reg, uint8_t data)
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{
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switch (reg) {
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case PCA9554_OUTPUT:
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case PCA9554_CONFIG:
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s->regs[reg] = data;
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pca9554_update_pin_input(s);
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break;
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case PCA9554_POLARITY:
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s->regs[reg] = data;
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break;
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case PCA9554_INPUT:
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: unexpected write to register %d\n",
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__func__, reg);
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}
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}
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static uint8_t pca9554_recv(I2CSlave *i2c)
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{
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PCA9554State *s = PCA9554(i2c);
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uint8_t ret;
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ret = pca9554_read(s, s->pointer & 0x3);
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return ret;
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}
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static int pca9554_send(I2CSlave *i2c, uint8_t data)
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{
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PCA9554State *s = PCA9554(i2c);
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/* First byte sent by is the register address */
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if (s->len == 0) {
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s->pointer = data;
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s->len++;
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} else {
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pca9554_write(s, s->pointer & 0x3, data);
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}
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return 0;
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}
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static int pca9554_event(I2CSlave *i2c, enum i2c_event event)
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{
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PCA9554State *s = PCA9554(i2c);
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s->len = 0;
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return 0;
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}
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static void pca9554_get_pin(Object *obj, Visitor *v, const char *name,
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void *opaque, Error **errp)
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{
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PCA9554State *s = PCA9554(obj);
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int pin, rc;
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uint8_t state;
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rc = sscanf(name, "pin%2d", &pin);
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if (rc != 1) {
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error_setg(errp, "%s: error reading %s", __func__, name);
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return;
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}
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if (pin < 0 || pin > PCA9554_PIN_COUNT) {
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error_setg(errp, "%s invalid pin %s", __func__, name);
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return;
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}
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state = pca9554_read(s, PCA9554_CONFIG);
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state |= pca9554_read(s, PCA9554_OUTPUT);
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state = (state >> pin) & 0x1;
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visit_type_str(v, name, (char **)&pin_state[state], errp);
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}
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static void pca9554_set_pin(Object *obj, Visitor *v, const char *name,
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void *opaque, Error **errp)
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{
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PCA9554State *s = PCA9554(obj);
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int pin, rc, val;
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uint8_t state, mask;
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char *state_str;
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if (!visit_type_str(v, name, &state_str, errp)) {
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return;
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}
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rc = sscanf(name, "pin%2d", &pin);
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if (rc != 1) {
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error_setg(errp, "%s: error reading %s", __func__, name);
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return;
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}
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if (pin < 0 || pin > PCA9554_PIN_COUNT) {
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error_setg(errp, "%s invalid pin %s", __func__, name);
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return;
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}
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for (state = 0; state < ARRAY_SIZE(pin_state); state++) {
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if (!strcmp(state_str, pin_state[state])) {
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break;
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}
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}
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if (state >= ARRAY_SIZE(pin_state)) {
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error_setg(errp, "%s invalid pin state %s", __func__, state_str);
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return;
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}
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/* First, modify the output register bit */
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val = pca9554_read(s, PCA9554_OUTPUT);
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mask = 0x1 << pin;
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if (state == PCA9554_PIN_LOW) {
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val &= ~(mask);
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} else {
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val |= mask;
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}
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pca9554_write(s, PCA9554_OUTPUT, val);
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/* Then, clear the config register bit for output mode */
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val = pca9554_read(s, PCA9554_CONFIG);
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val &= ~mask;
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pca9554_write(s, PCA9554_CONFIG, val);
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}
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static const VMStateDescription pca9554_vmstate = {
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.name = "PCA9554",
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.version_id = 0,
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.minimum_version_id = 0,
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.fields = (VMStateField[]) {
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VMSTATE_UINT8(len, PCA9554State),
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VMSTATE_UINT8(pointer, PCA9554State),
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VMSTATE_UINT8_ARRAY(regs, PCA9554State, PCA9554_NR_REGS),
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VMSTATE_UINT8_ARRAY(ext_state, PCA9554State, PCA9554_PIN_COUNT),
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VMSTATE_I2C_SLAVE(i2c, PCA9554State),
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VMSTATE_END_OF_LIST()
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}
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};
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static void pca9554_reset(DeviceState *dev)
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{
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PCA9554State *s = PCA9554(dev);
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s->regs[PCA9554_INPUT] = 0xFF;
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s->regs[PCA9554_OUTPUT] = 0xFF;
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s->regs[PCA9554_POLARITY] = 0x0; /* No pins are inverted */
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s->regs[PCA9554_CONFIG] = 0xFF; /* All pins are inputs */
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memset(s->ext_state, PCA9554_PIN_HIZ, PCA9554_PIN_COUNT);
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pca9554_update_pin_input(s);
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s->pointer = 0x0;
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s->len = 0;
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}
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static void pca9554_initfn(Object *obj)
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{
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int pin;
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for (pin = 0; pin < PCA9554_PIN_COUNT; pin++) {
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char *name;
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name = g_strdup_printf("pin%d", pin);
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object_property_add(obj, name, "bool", pca9554_get_pin, pca9554_set_pin,
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NULL, NULL);
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g_free(name);
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}
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}
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static void pca9554_set_ext_state(PCA9554State *s, int pin, int level)
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{
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if (s->ext_state[pin] != level) {
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s->ext_state[pin] = level;
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pca9554_update_pin_input(s);
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}
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}
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static void pca9554_gpio_in_handler(void *opaque, int pin, int level)
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{
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PCA9554State *s = PCA9554(opaque);
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assert((pin >= 0) && (pin < PCA9554_PIN_COUNT));
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pca9554_set_ext_state(s, pin, level);
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}
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static void pca9554_realize(DeviceState *dev, Error **errp)
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{
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PCA9554State *s = PCA9554(dev);
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if (!s->description) {
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s->description = g_strdup("pca9554");
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}
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qdev_init_gpio_out(dev, s->gpio_out, PCA9554_PIN_COUNT);
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qdev_init_gpio_in(dev, pca9554_gpio_in_handler, PCA9554_PIN_COUNT);
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}
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static Property pca9554_properties[] = {
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DEFINE_PROP_STRING("description", PCA9554State, description),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void pca9554_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
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k->event = pca9554_event;
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k->recv = pca9554_recv;
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k->send = pca9554_send;
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dc->realize = pca9554_realize;
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dc->reset = pca9554_reset;
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dc->vmsd = &pca9554_vmstate;
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device_class_set_props(dc, pca9554_properties);
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}
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static const TypeInfo pca9554_info = {
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.name = TYPE_PCA9554,
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.parent = TYPE_I2C_SLAVE,
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.instance_init = pca9554_initfn,
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.instance_size = sizeof(PCA9554State),
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.class_init = pca9554_class_init,
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.class_size = sizeof(PCA9554Class),
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.abstract = false,
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};
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static void pca9554_register_types(void)
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{
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type_register_static(&pca9554_info);
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}
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type_init(pca9554_register_types)
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36
include/hw/misc/pca9554.h
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36
include/hw/misc/pca9554.h
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@ -0,0 +1,36 @@
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/*
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* PCA9554 I/O port
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*
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* Copyright (c) 2023, IBM Corporation.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef PCA9554_H
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#define PCA9554_H
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#include "hw/i2c/i2c.h"
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#include "qom/object.h"
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#define TYPE_PCA9554 "pca9554"
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typedef struct PCA9554State PCA9554State;
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DECLARE_INSTANCE_CHECKER(PCA9554State, PCA9554,
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TYPE_PCA9554)
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#define PCA9554_NR_REGS 4
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#define PCA9554_PIN_COUNT 8
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struct PCA9554State {
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/*< private >*/
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I2CSlave i2c;
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/*< public >*/
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uint8_t len;
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uint8_t pointer;
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uint8_t regs[PCA9554_NR_REGS];
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qemu_irq gpio_out[PCA9554_PIN_COUNT];
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uint8_t ext_state[PCA9554_PIN_COUNT];
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char *description; /* For debugging purpose only */
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};
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#endif
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19
include/hw/misc/pca9554_regs.h
Normal file
19
include/hw/misc/pca9554_regs.h
Normal file
@ -0,0 +1,19 @@
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/*
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* PCA9554 I/O port registers
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*
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* Copyright (c) 2023, IBM Corporation.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef PCA9554_REGS_H
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#define PCA9554_REGS_H
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/*
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* Bits [0:1] are used to address a specific register.
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*/
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#define PCA9554_INPUT 0 /* read only input register */
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#define PCA9554_OUTPUT 1 /* read/write pin output state */
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#define PCA9554_POLARITY 2 /* Set polarity of input register */
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#define PCA9554_CONFIG 3 /* Set pins as inputs our ouputs */
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#endif
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