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target/arm: Implement SVE prefetches 

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180627043328.11531-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2018-06-29 15:11:06 +01:00 committed by Peter Maydell
parent f6dbf62a7e
commit dec6cf6b43
2 changed files with 44 additions and 0 deletions
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23
target/arm/sve.decode
View File

@ -794,6 +794,29 @@ LD1RQ_zprr 1010010 .. 00 ..... 000 ... ..... ..... \
LD1RQ_zpri 1010010 .. 00 0.... 001 ... ..... ..... \
@rpri_load_msz nreg=0
# SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets)
PRF 1000010 00 -1 ----- 0-- --- ----- 0 ----
# SVE 32-bit gather prefetch (vector plus immediate)
PRF 1000010 -- 00 ----- 111 --- ----- 0 ----
# SVE contiguous prefetch (scalar plus immediate)
PRF 1000010 11 1- ----- 0-- --- ----- 0 ----
# SVE contiguous prefetch (scalar plus scalar)
PRF_rr 1000010 -- 00 rm:5 110 --- ----- 0 ----
### SVE Memory 64-bit Gather Group
# SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets)
PRF 1100010 00 11 ----- 1-- --- ----- 0 ----
# SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets)
PRF 1100010 00 -1 ----- 0-- --- ----- 0 ----
# SVE 64-bit gather prefetch (vector plus immediate)
PRF 1100010 -- 00 ----- 111 --- ----- 0 ----
### SVE Memory Store Group
# SVE store predicate register

21
target/arm/translate-sve.c
View File

@ -4303,3 +4303,24 @@ static bool trans_ST1_zprz(DisasContext *s, arg_ST1_zprz *a, uint32_t insn)
cpu_reg_sp(s, a->rn), fn);
return true;
}
/*
* Prefetches
*/
static bool trans_PRF(DisasContext *s, arg_PRF *a, uint32_t insn)
{
/* Prefetch is a nop within QEMU. */
sve_access_check(s);
return true;
}
static bool trans_PRF_rr(DisasContext *s, arg_PRF_rr *a, uint32_t insn)
{
if (a->rm == 31) {
return false;
}
/* Prefetch is a nop within QEMU. */
sve_access_check(s);
return true;
}