From dedc53cbc9f267e2ad037218ab07f9b4097efa65 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Fri, 10 Dec 2021 15:56:22 +0800 Subject: [PATCH] target/riscv: rvv-1.0: integer scalar move instructions * Remove "vmv.s.x: dothing if rs1 == 0" constraint. * Add vmv.x.s instruction. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Acked-by: Alistair Francis Message-Id: <20211210075704.23951-37-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 3 +- target/riscv/insn_trans/trans_rvv.c.inc | 43 ++++++++++++++++++++----- 2 files changed, 37 insertions(+), 9 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 4653a9679e..e33ec82fdf 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -634,8 +634,9 @@ vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm +vmv_x_s 010000 1 ..... 00000 010 ..... 1010111 @r2rd +vmv_s_x 010000 1 00000 ..... 110 ..... 1010111 @r2 vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r -vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2 vfmv_f_s 001100 1 ..... 00000 001 ..... 1010111 @r2rd vfmv_s_f 001101 1 00000 ..... 101 ..... 1010111 @r2 vslideup_vx 001110 . ..... ..... 100 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 322fc5c4aa..c250943dde 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2978,27 +2978,54 @@ static void vec_element_storei(DisasContext *s, int vreg, store_element(val, cpu_env, endian_ofs(s, vreg, idx), s->sew); } +/* vmv.x.s rd, vs2 # x[rd] = vs2[0] */ +static bool trans_vmv_x_s(DisasContext *s, arg_vmv_x_s *a) +{ + if (require_rvv(s) && + vext_check_isa_ill(s)) { + TCGv_i64 t1; + TCGv dest; + + t1 = tcg_temp_new_i64(); + dest = tcg_temp_new(); + /* + * load vreg and sign-extend to 64 bits, + * then truncate to XLEN bits before storing to gpr. + */ + vec_element_loadi(s, t1, a->rs2, 0, true); + tcg_gen_trunc_i64_tl(dest, t1); + gen_set_gpr(s, a->rd, dest); + tcg_temp_free_i64(t1); + tcg_temp_free(dest); + + return true; + } + return false; +} + /* vmv.s.x vd, rs1 # vd[0] = rs1 */ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a) { - if (vext_check_isa_ill(s)) { + if (require_rvv(s) && + vext_check_isa_ill(s)) { /* This instruction ignores LMUL and vector register groups */ - int maxsz = s->vlen >> 3; TCGv_i64 t1; + TCGv s1; TCGLabel *over = gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), maxsz, maxsz, 0); - if (a->rs1 == 0) { - goto done; - } t1 = tcg_temp_new_i64(); - tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]); + + /* + * load gpr and sign-extend to 64 bits, + * then truncate to SEW bits when storing to vreg. + */ + s1 = get_gpr(s, a->rs1, EXT_NONE); + tcg_gen_ext_tl_i64(t1, s1); vec_element_storei(s, a->rd, 0, t1); tcg_temp_free_i64(t1); mark_vs_dirty(s); - done: gen_set_label(over); return true; }