ppc/pnv: move PCI registers to PnvPHB4
Previous patch changed pnv_pec_stk_pci_xscom_read() and pnv_pec_stk_pci_xscom_write() to use a PnvPHB4 opaque, making it easier to move both pci_regs[] and the pci_regs_mr MemoryRegion to the PnvHB4 object. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220113192952.911188-3-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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@ -1071,54 +1071,54 @@ static const MemoryRegionOps pnv_pec_stk_nest_xscom_ops = {
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static uint64_t pnv_pec_stk_pci_xscom_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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PnvPhb4PecStack *stack = PNV_PHB4(opaque)->stack;
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PnvPHB4 *phb = PNV_PHB4(opaque);
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uint32_t reg = addr >> 3;
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/* TODO: add list of allowed registers and error out if not */
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return stack->pci_regs[reg];
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return phb->pci_regs[reg];
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}
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static void pnv_pec_stk_pci_xscom_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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PnvPhb4PecStack *stack = PNV_PHB4(opaque)->stack;
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PnvPHB4 *phb = PNV_PHB4(opaque);
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uint32_t reg = addr >> 3;
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switch (reg) {
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case PEC_PCI_STK_PCI_FIR:
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stack->pci_regs[reg] = val;
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phb->pci_regs[reg] = val;
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break;
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case PEC_PCI_STK_PCI_FIR_CLR:
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stack->pci_regs[PEC_PCI_STK_PCI_FIR] &= val;
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phb->pci_regs[PEC_PCI_STK_PCI_FIR] &= val;
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break;
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case PEC_PCI_STK_PCI_FIR_SET:
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stack->pci_regs[PEC_PCI_STK_PCI_FIR] |= val;
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phb->pci_regs[PEC_PCI_STK_PCI_FIR] |= val;
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break;
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case PEC_PCI_STK_PCI_FIR_MSK:
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stack->pci_regs[reg] = val;
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phb->pci_regs[reg] = val;
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break;
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case PEC_PCI_STK_PCI_FIR_MSKC:
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stack->pci_regs[PEC_PCI_STK_PCI_FIR_MSK] &= val;
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phb->pci_regs[PEC_PCI_STK_PCI_FIR_MSK] &= val;
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break;
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case PEC_PCI_STK_PCI_FIR_MSKS:
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stack->pci_regs[PEC_PCI_STK_PCI_FIR_MSK] |= val;
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phb->pci_regs[PEC_PCI_STK_PCI_FIR_MSK] |= val;
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break;
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case PEC_PCI_STK_PCI_FIR_ACT0:
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case PEC_PCI_STK_PCI_FIR_ACT1:
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stack->pci_regs[reg] = val;
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phb->pci_regs[reg] = val;
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break;
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case PEC_PCI_STK_PCI_FIR_WOF:
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stack->pci_regs[reg] = 0;
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phb->pci_regs[reg] = 0;
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break;
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case PEC_PCI_STK_ETU_RESET:
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stack->pci_regs[reg] = val & 0x8000000000000000ull;
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phb->pci_regs[reg] = val & 0x8000000000000000ull;
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/* TODO: Implement reset */
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break;
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case PEC_PCI_STK_PBAIB_ERR_REPORT:
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break;
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case PEC_PCI_STK_PBAIB_TX_CMD_CRED:
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case PEC_PCI_STK_PBAIB_TX_DAT_CRED:
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stack->pci_regs[reg] = val;
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phb->pci_regs[reg] = val;
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "phb4_pec_stk: pci_xscom_write 0x%"HWADDR_PRIx
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@ -1477,7 +1477,7 @@ static void pnv_phb4_xscom_realize(PnvPHB4 *phb)
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snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci-phb-%d",
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pec->chip_id, pec->index, stack->stack_no);
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pnv_xscom_region_init(&stack->pci_regs_mr, OBJECT(phb),
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pnv_xscom_region_init(&phb->pci_regs_mr, OBJECT(phb),
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&pnv_pec_stk_pci_xscom_ops, phb, name,
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PHB4_PEC_PCI_STK_REGS_COUNT);
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@ -1496,7 +1496,7 @@ static void pnv_phb4_xscom_realize(PnvPHB4 *phb)
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&stack->nest_regs_mr);
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pnv_xscom_add_subregion(pec->chip,
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pec_pci_base + 0x40 * (stack->stack_no + 1),
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&stack->pci_regs_mr);
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&phb->pci_regs_mr);
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pnv_xscom_add_subregion(pec->chip,
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pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 +
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0x40 * stack->stack_no,
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@ -107,6 +107,11 @@ struct PnvPHB4 {
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MemoryRegion pci_mmio;
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MemoryRegion pci_io;
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/* PCI registers (excluding pass-through) */
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#define PHB4_PEC_PCI_STK_REGS_COUNT 0xf
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uint64_t pci_regs[PHB4_PEC_PCI_STK_REGS_COUNT];
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MemoryRegion pci_regs_mr;
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/* On-chip IODA tables */
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uint64_t ioda_LIST[PNV_PHB4_MAX_LSIs];
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uint64_t ioda_MIST[PNV_PHB4_MAX_MIST];
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@ -155,11 +160,6 @@ struct PnvPhb4PecStack {
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uint64_t nest_regs[PHB4_PEC_NEST_STK_REGS_COUNT];
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MemoryRegion nest_regs_mr;
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/* PCI registers (excluding pass-through) */
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#define PHB4_PEC_PCI_STK_REGS_COUNT 0xf
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uint64_t pci_regs[PHB4_PEC_PCI_STK_REGS_COUNT];
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MemoryRegion pci_regs_mr;
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/* PHB pass-through XSCOM */
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MemoryRegion phb_regs_mr;
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