tcg-arm: Convert to CONFIG_QEMU_LDST_OPTIMIZATION
Move the slow path out of line, as the TODO's mention. This allows the fast path to be unconditional, which can speed up the fast path as well, depending on the core. Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
Aurelien Jarno
parent
302fdde73f
commit
df5e0ef711
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@ -3609,7 +3609,7 @@ echo "libs_softmmu=$libs_softmmu" >> $config_host_mak
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echo "ARCH=$ARCH" >> $config_host_mak
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case "$cpu" in
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i386|x86_64|ppc)
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arm|i386|x86_64|ppc)
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# The TCG interpreter currently does not support ld/st optimization.
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if test "$tcg_interpreter" = "no" ; then
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echo "CONFIG_QEMU_LDST_OPTIMIZATION=y" >> $config_host_mak
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@ -338,6 +338,23 @@ extern uintptr_t tci_tb_ptr;
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# elif defined (_ARCH_PPC) && !defined (_ARCH_PPC64)
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# define GETRA() ((uintptr_t)__builtin_return_address(0))
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# define GETPC_LDST() ((uintptr_t) ((*(int32_t *)(GETRA() - 4)) - 1))
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# elif defined(__arm__)
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/* We define two insns between the return address and the branch back to
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straight-line. Find and decode that branch insn. */
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# define GETRA() ((uintptr_t)__builtin_return_address(0))
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# define GETPC_LDST() tcg_getpc_ldst(GETRA())
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static inline uintptr_t tcg_getpc_ldst(uintptr_t ra)
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{
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int32_t b;
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ra += 8; /* skip the two insns */
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b = *(int32_t *)ra; /* load the branch insn */
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b = (b << 8) >> (8 - 2); /* extract the displacement */
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ra += 8; /* branches are relative to pc+8 */
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ra += b; /* apply the displacement */
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ra -= 4; /* return a pointer into the current opcode,
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not the start of the next opcode */
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return ra;
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}
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# else
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# error "CONFIG_QEMU_LDST_OPTIMIZATION needs GETPC_LDST() implementation!"
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# endif
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@ -419,6 +419,20 @@ static inline void tcg_out_dat_reg(TCGContext *s,
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(rn << 16) | (rd << 12) | shift | rm);
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}
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static inline void tcg_out_nop(TCGContext *s)
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{
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if (use_armv7_instructions) {
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/* Architected nop introduced in v6k. */
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/* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this
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also Just So Happened to do nothing on pre-v6k so that we
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don't need to conditionalize it? */
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tcg_out32(s, 0xe320f000);
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} else {
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/* Prior to that the assembler uses mov r0, r0. */
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tcg_out_dat_reg(s, COND_AL, ARITH_MOV, 0, 0, 0, SHIFT_IMM_LSL(0));
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}
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}
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static inline void tcg_out_mov_reg(TCGContext *s, int cond, int rd, int rm)
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{
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/* Simple reg-reg move, optimising out the 'do nothing' case */
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@ -1200,98 +1214,56 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
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TCG_REG_R1, addrhi, SHIFT_IMM_LSL(0));
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}
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}
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#endif /* SOFTMMU */
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static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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/* Record the context of a call to the out of line helper code for the slow
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path for a load or store, so that we can later generate the correct
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helper code. */
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static void add_qemu_ldst_label(TCGContext *s, int is_ld, int opc,
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int data_reg, int data_reg2, int addrlo_reg,
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int addrhi_reg, int mem_index,
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uint8_t *raddr, uint8_t *label_ptr)
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{
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TCGReg addr_reg, data_reg, data_reg2;
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bool bswap;
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#ifdef CONFIG_SOFTMMU
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int mem_index, s_bits;
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TCGReg argreg, addr_reg2;
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uint32_t *label_ptr;
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#endif
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#ifdef TARGET_WORDS_BIGENDIAN
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bswap = 1;
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#else
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bswap = 0;
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#endif
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int idx;
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TCGLabelQemuLdst *label;
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data_reg = *args++;
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data_reg2 = (opc == 3 ? *args++ : 0);
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addr_reg = *args++;
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#ifdef CONFIG_SOFTMMU
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addr_reg2 = (TARGET_LONG_BITS == 64 ? *args++ : 0);
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mem_index = *args;
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s_bits = opc & 3;
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tcg_out_tlb_read(s, addr_reg, addr_reg2, s_bits,
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offsetof(CPUArchState, tlb_table[mem_index][0].addr_read));
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tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R2,
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offsetof(CPUTLBEntry, addend)
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- offsetof(CPUTLBEntry, addr_read));
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switch (opc) {
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case 0:
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tcg_out_ld8_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
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break;
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case 0 | 4:
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tcg_out_ld8s_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
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break;
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case 1:
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tcg_out_ld16u_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
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if (bswap) {
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tcg_out_bswap16(s, COND_EQ, data_reg, data_reg);
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}
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break;
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case 1 | 4:
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if (bswap) {
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tcg_out_ld16u_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
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tcg_out_bswap16s(s, COND_EQ, data_reg, data_reg);
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} else {
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tcg_out_ld16s_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
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}
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break;
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case 2:
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default:
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tcg_out_ld32_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
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if (bswap) {
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tcg_out_bswap32(s, COND_EQ, data_reg, data_reg);
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}
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break;
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case 3:
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if (bswap) {
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tcg_out_ld32_rwb(s, COND_EQ, data_reg2, TCG_REG_R1, addr_reg);
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tcg_out_ld32_12(s, COND_EQ, data_reg, TCG_REG_R1, 4);
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tcg_out_bswap32(s, COND_EQ, data_reg2, data_reg2);
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tcg_out_bswap32(s, COND_EQ, data_reg, data_reg);
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} else {
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tcg_out_ld32_rwb(s, COND_EQ, data_reg, TCG_REG_R1, addr_reg);
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tcg_out_ld32_12(s, COND_EQ, data_reg2, TCG_REG_R1, 4);
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}
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break;
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if (s->nb_qemu_ldst_labels >= TCG_MAX_QEMU_LDST) {
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tcg_abort();
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}
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label_ptr = (void *) s->code_ptr;
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tcg_out_b_noaddr(s, COND_EQ);
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idx = s->nb_qemu_ldst_labels++;
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label = (TCGLabelQemuLdst *)&s->qemu_ldst_labels[idx];
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label->is_ld = is_ld;
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label->opc = opc;
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label->datalo_reg = data_reg;
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label->datahi_reg = data_reg2;
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label->addrlo_reg = addrlo_reg;
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label->addrhi_reg = addrhi_reg;
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label->mem_index = mem_index;
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label->raddr = raddr;
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label->label_ptr[0] = label_ptr;
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}
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/* TODO: move this code to where the constants pool will be */
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/* Note that this code relies on the constraints we set in arm_op_defs[]
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* to ensure that later arguments are not passed to us in registers we
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* trash by moving the earlier arguments into them.
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*/
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argreg = TCG_REG_R0;
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argreg = tcg_out_arg_reg32(s, argreg, TCG_AREG0);
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static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
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{
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TCGReg argreg, data_reg, data_reg2;
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uint8_t *start;
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reloc_pc24(lb->label_ptr[0], (tcg_target_long)s->code_ptr);
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argreg = tcg_out_arg_reg32(s, TCG_REG_R0, TCG_AREG0);
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if (TARGET_LONG_BITS == 64) {
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argreg = tcg_out_arg_reg64(s, argreg, addr_reg, addr_reg2);
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argreg = tcg_out_arg_reg64(s, argreg, lb->addrlo_reg, lb->addrhi_reg);
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} else {
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argreg = tcg_out_arg_reg32(s, argreg, addr_reg);
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argreg = tcg_out_arg_reg32(s, argreg, lb->addrlo_reg);
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}
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argreg = tcg_out_arg_imm32(s, argreg, mem_index);
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tcg_out_call(s, (tcg_target_long) qemu_ld_helpers[s_bits]);
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argreg = tcg_out_arg_imm32(s, argreg, lb->mem_index);
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tcg_out_call(s, (tcg_target_long) qemu_ld_helpers[lb->opc & 3]);
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switch (opc) {
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data_reg = lb->datalo_reg;
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data_reg2 = lb->datahi_reg;
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start = s->code_ptr;
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switch (lb->opc) {
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case 0 | 4:
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tcg_out_ext8s(s, COND_AL, data_reg, TCG_REG_R0);
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break;
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@ -1310,7 +1282,144 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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break;
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}
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reloc_pc24(label_ptr, (tcg_target_long)s->code_ptr);
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/* For GETPC_LDST in exec-all.h, we architect exactly 2 insns between
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the call and the branch back to straight-line code. Note that the
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moves above could be elided by register allocation, nor do we know
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which code alternative we chose for extension. */
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switch (s->code_ptr - start) {
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case 0:
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tcg_out_nop(s);
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/* FALLTHRU */
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case 4:
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tcg_out_nop(s);
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/* FALLTHRU */
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case 8:
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break;
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default:
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abort();
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}
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tcg_out_goto(s, COND_AL, (tcg_target_long)lb->raddr);
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}
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static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
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{
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TCGReg argreg, data_reg, data_reg2;
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reloc_pc24(lb->label_ptr[0], (tcg_target_long)s->code_ptr);
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argreg = TCG_REG_R0;
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argreg = tcg_out_arg_reg32(s, argreg, TCG_AREG0);
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if (TARGET_LONG_BITS == 64) {
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argreg = tcg_out_arg_reg64(s, argreg, lb->addrlo_reg, lb->addrhi_reg);
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} else {
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argreg = tcg_out_arg_reg32(s, argreg, lb->addrlo_reg);
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}
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data_reg = lb->datalo_reg;
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data_reg2 = lb->datahi_reg;
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switch (lb->opc) {
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case 0:
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argreg = tcg_out_arg_reg8(s, argreg, data_reg);
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break;
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case 1:
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argreg = tcg_out_arg_reg16(s, argreg, data_reg);
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break;
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case 2:
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argreg = tcg_out_arg_reg32(s, argreg, data_reg);
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break;
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case 3:
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argreg = tcg_out_arg_reg64(s, argreg, data_reg, data_reg2);
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break;
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}
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argreg = tcg_out_arg_imm32(s, argreg, lb->mem_index);
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tcg_out_call(s, (tcg_target_long) qemu_st_helpers[lb->opc & 3]);
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/* For GETPC_LDST in exec-all.h, we architect exactly 2 insns between
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the call and the branch back to straight-line code. */
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tcg_out_nop(s);
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tcg_out_nop(s);
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tcg_out_goto(s, COND_AL, (tcg_target_long)lb->raddr);
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}
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#endif /* SOFTMMU */
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static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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{
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TCGReg addr_reg, data_reg, data_reg2;
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bool bswap;
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#ifdef CONFIG_SOFTMMU
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int mem_index, s_bits;
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TCGReg addr_reg2;
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uint8_t *label_ptr;
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#endif
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#ifdef TARGET_WORDS_BIGENDIAN
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bswap = 1;
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#else
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bswap = 0;
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#endif
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data_reg = *args++;
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data_reg2 = (opc == 3 ? *args++ : 0);
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addr_reg = *args++;
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#ifdef CONFIG_SOFTMMU
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addr_reg2 = (TARGET_LONG_BITS == 64 ? *args++ : 0);
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mem_index = *args;
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s_bits = opc & 3;
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tcg_out_tlb_read(s, addr_reg, addr_reg2, s_bits,
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offsetof(CPUArchState, tlb_table[mem_index][0].addr_read));
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label_ptr = s->code_ptr;
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tcg_out_b_noaddr(s, COND_NE);
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tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R2,
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offsetof(CPUTLBEntry, addend)
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- offsetof(CPUTLBEntry, addr_read));
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switch (opc) {
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case 0:
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tcg_out_ld8_r(s, COND_AL, data_reg, addr_reg, TCG_REG_R1);
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break;
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case 0 | 4:
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tcg_out_ld8s_r(s, COND_AL, data_reg, addr_reg, TCG_REG_R1);
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break;
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case 1:
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tcg_out_ld16u_r(s, COND_AL, data_reg, addr_reg, TCG_REG_R1);
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if (bswap) {
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tcg_out_bswap16(s, COND_AL, data_reg, data_reg);
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}
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break;
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case 1 | 4:
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if (bswap) {
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tcg_out_ld16u_r(s, COND_AL, data_reg, addr_reg, TCG_REG_R1);
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tcg_out_bswap16s(s, COND_AL, data_reg, data_reg);
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} else {
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tcg_out_ld16s_r(s, COND_AL, data_reg, addr_reg, TCG_REG_R1);
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}
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break;
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case 2:
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default:
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tcg_out_ld32_r(s, COND_AL, data_reg, addr_reg, TCG_REG_R1);
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if (bswap) {
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tcg_out_bswap32(s, COND_AL, data_reg, data_reg);
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}
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break;
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case 3:
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if (bswap) {
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tcg_out_ld32_rwb(s, COND_AL, data_reg2, TCG_REG_R1, addr_reg);
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tcg_out_ld32_12(s, COND_AL, data_reg, TCG_REG_R1, 4);
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tcg_out_bswap32(s, COND_AL, data_reg2, data_reg2);
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tcg_out_bswap32(s, COND_AL, data_reg, data_reg);
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} else {
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tcg_out_ld32_rwb(s, COND_AL, data_reg, TCG_REG_R1, addr_reg);
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tcg_out_ld32_12(s, COND_AL, data_reg2, TCG_REG_R1, 4);
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}
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break;
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}
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add_qemu_ldst_label(s, 1, opc, data_reg, data_reg2, addr_reg, addr_reg2,
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mem_index, s->code_ptr, label_ptr);
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#else /* !CONFIG_SOFTMMU */
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if (GUEST_BASE) {
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uint32_t offset = GUEST_BASE;
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@ -1379,8 +1488,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
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bool bswap;
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#ifdef CONFIG_SOFTMMU
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int mem_index, s_bits;
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TCGReg argreg, addr_reg2;
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uint32_t *label_ptr;
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TCGReg addr_reg2;
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uint8_t *label_ptr;
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#endif
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#ifdef TARGET_WORDS_BIGENDIAN
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bswap = 1;
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@ -1400,79 +1509,49 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
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offsetof(CPUArchState,
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tlb_table[mem_index][0].addr_write));
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tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R2,
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label_ptr = s->code_ptr;
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tcg_out_b_noaddr(s, COND_NE);
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tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R2,
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offsetof(CPUTLBEntry, addend)
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- offsetof(CPUTLBEntry, addr_write));
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switch (opc) {
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case 0:
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tcg_out_st8_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
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tcg_out_st8_r(s, COND_AL, data_reg, addr_reg, TCG_REG_R1);
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break;
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case 1:
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if (bswap) {
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tcg_out_bswap16st(s, COND_EQ, TCG_REG_R0, data_reg);
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tcg_out_st16_r(s, COND_EQ, TCG_REG_R0, addr_reg, TCG_REG_R1);
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tcg_out_bswap16st(s, COND_AL, TCG_REG_R0, data_reg);
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tcg_out_st16_r(s, COND_AL, TCG_REG_R0, addr_reg, TCG_REG_R1);
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} else {
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tcg_out_st16_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
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tcg_out_st16_r(s, COND_AL, data_reg, addr_reg, TCG_REG_R1);
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}
|
||||
break;
|
||||
case 2:
|
||||
default:
|
||||
if (bswap) {
|
||||
tcg_out_bswap32(s, COND_EQ, TCG_REG_R0, data_reg);
|
||||
tcg_out_st32_r(s, COND_EQ, TCG_REG_R0, addr_reg, TCG_REG_R1);
|
||||
tcg_out_bswap32(s, COND_AL, TCG_REG_R0, data_reg);
|
||||
tcg_out_st32_r(s, COND_AL, TCG_REG_R0, addr_reg, TCG_REG_R1);
|
||||
} else {
|
||||
tcg_out_st32_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1);
|
||||
tcg_out_st32_r(s, COND_AL, data_reg, addr_reg, TCG_REG_R1);
|
||||
}
|
||||
break;
|
||||
case 3:
|
||||
if (bswap) {
|
||||
tcg_out_bswap32(s, COND_EQ, TCG_REG_R0, data_reg2);
|
||||
tcg_out_st32_rwb(s, COND_EQ, TCG_REG_R0, TCG_REG_R1, addr_reg);
|
||||
tcg_out_bswap32(s, COND_EQ, TCG_REG_R0, data_reg);
|
||||
tcg_out_st32_12(s, COND_EQ, TCG_REG_R0, TCG_REG_R1, 4);
|
||||
tcg_out_bswap32(s, COND_AL, TCG_REG_R0, data_reg2);
|
||||
tcg_out_st32_rwb(s, COND_AL, TCG_REG_R0, TCG_REG_R1, addr_reg);
|
||||
tcg_out_bswap32(s, COND_AL, TCG_REG_R0, data_reg);
|
||||
tcg_out_st32_12(s, COND_AL, TCG_REG_R0, TCG_REG_R1, 4);
|
||||
} else {
|
||||
tcg_out_st32_rwb(s, COND_EQ, data_reg, TCG_REG_R1, addr_reg);
|
||||
tcg_out_st32_12(s, COND_EQ, data_reg2, TCG_REG_R1, 4);
|
||||
tcg_out_st32_rwb(s, COND_AL, data_reg, TCG_REG_R1, addr_reg);
|
||||
tcg_out_st32_12(s, COND_AL, data_reg2, TCG_REG_R1, 4);
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
label_ptr = (void *) s->code_ptr;
|
||||
tcg_out_b_noaddr(s, COND_EQ);
|
||||
|
||||
/* TODO: move this code to where the constants pool will be */
|
||||
/* Note that this code relies on the constraints we set in arm_op_defs[]
|
||||
* to ensure that later arguments are not passed to us in registers we
|
||||
* trash by moving the earlier arguments into them.
|
||||
*/
|
||||
argreg = TCG_REG_R0;
|
||||
argreg = tcg_out_arg_reg32(s, argreg, TCG_AREG0);
|
||||
if (TARGET_LONG_BITS == 64) {
|
||||
argreg = tcg_out_arg_reg64(s, argreg, addr_reg, addr_reg2);
|
||||
} else {
|
||||
argreg = tcg_out_arg_reg32(s, argreg, addr_reg);
|
||||
}
|
||||
|
||||
switch (opc) {
|
||||
case 0:
|
||||
argreg = tcg_out_arg_reg8(s, argreg, data_reg);
|
||||
break;
|
||||
case 1:
|
||||
argreg = tcg_out_arg_reg16(s, argreg, data_reg);
|
||||
break;
|
||||
case 2:
|
||||
argreg = tcg_out_arg_reg32(s, argreg, data_reg);
|
||||
break;
|
||||
case 3:
|
||||
argreg = tcg_out_arg_reg64(s, argreg, data_reg, data_reg2);
|
||||
break;
|
||||
}
|
||||
|
||||
argreg = tcg_out_arg_imm32(s, argreg, mem_index);
|
||||
tcg_out_call(s, (tcg_target_long) qemu_st_helpers[s_bits]);
|
||||
|
||||
reloc_pc24(label_ptr, (tcg_target_long)s->code_ptr);
|
||||
add_qemu_ldst_label(s, 0, opc, data_reg, data_reg2, addr_reg, addr_reg2,
|
||||
mem_index, s->code_ptr, label_ptr);
|
||||
#else /* !CONFIG_SOFTMMU */
|
||||
if (GUEST_BASE) {
|
||||
uint32_t offset = GUEST_BASE;
|
||||
|
|
@ -1872,6 +1951,22 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
|
|||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SOFTMMU
|
||||
/* Generate TB finalization at the end of block. */
|
||||
void tcg_out_tb_finalize(TCGContext *s)
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < s->nb_qemu_ldst_labels; i++) {
|
||||
TCGLabelQemuLdst *label = &s->qemu_ldst_labels[i];
|
||||
if (label->is_ld) {
|
||||
tcg_out_qemu_ld_slow_path(s, label);
|
||||
} else {
|
||||
tcg_out_qemu_st_slow_path(s, label);
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif /* SOFTMMU */
|
||||
|
||||
static const TCGTargetOpDef arm_op_defs[] = {
|
||||
{ INDEX_op_exit_tb, { } },
|
||||
{ INDEX_op_goto_tb, { } },
|
||||
|
|
|
|||
Loading…
Reference in New Issue