kvm: x86: fix setting IA32_FEATURE_CONTROL with nested VMX disabled
This patch is to fix the bug https://bugs.launchpad.net/qemu-kvm/+bug/1207623 IA32_FEATURE_CONTROL is pointless if not expose VMX or SMX bits to cpuid.1.ecx of vcpu. Current qemu-kvm will error return when kvm_put_msrs or kvm_get_msrs. Signed-off-by: Liu Jinsong <jinsong.liu@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -65,6 +65,7 @@ static bool has_msr_star;
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static bool has_msr_hsave_pa;
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static bool has_msr_hsave_pa;
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static bool has_msr_tsc_adjust;
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static bool has_msr_tsc_adjust;
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static bool has_msr_tsc_deadline;
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static bool has_msr_tsc_deadline;
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static bool has_msr_feature_control;
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static bool has_msr_async_pf_en;
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static bool has_msr_async_pf_en;
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static bool has_msr_pv_eoi_en;
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static bool has_msr_pv_eoi_en;
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static bool has_msr_misc_enable;
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static bool has_msr_misc_enable;
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@ -666,6 +667,12 @@ int kvm_arch_init_vcpu(CPUState *cs)
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qemu_add_vm_change_state_handler(cpu_update_state, env);
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qemu_add_vm_change_state_handler(cpu_update_state, env);
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c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
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if (c) {
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has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
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!!(c->ecx & CPUID_EXT_SMX);
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}
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cpuid_data.cpuid.padding = 0;
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cpuid_data.cpuid.padding = 0;
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r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
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r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
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if (r) {
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if (r) {
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@ -1169,7 +1176,10 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
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if (hyperv_vapic_recommended()) {
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if (hyperv_vapic_recommended()) {
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kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE, 0);
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kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE, 0);
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}
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}
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kvm_msr_entry_set(&msrs[n++], MSR_IA32_FEATURE_CONTROL, env->msr_ia32_feature_control);
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if (has_msr_feature_control) {
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kvm_msr_entry_set(&msrs[n++], MSR_IA32_FEATURE_CONTROL,
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env->msr_ia32_feature_control);
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}
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}
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}
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if (env->mcg_cap) {
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if (env->mcg_cap) {
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int i;
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int i;
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@ -1394,7 +1404,9 @@ static int kvm_get_msrs(X86CPU *cpu)
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if (has_msr_misc_enable) {
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if (has_msr_misc_enable) {
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msrs[n++].index = MSR_IA32_MISC_ENABLE;
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msrs[n++].index = MSR_IA32_MISC_ENABLE;
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}
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}
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msrs[n++].index = MSR_IA32_FEATURE_CONTROL;
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if (has_msr_feature_control) {
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msrs[n++].index = MSR_IA32_FEATURE_CONTROL;
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}
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if (!env->tsc_valid) {
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if (!env->tsc_valid) {
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msrs[n++].index = MSR_IA32_TSC;
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msrs[n++].index = MSR_IA32_TSC;
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@ -1509,6 +1521,7 @@ static int kvm_get_msrs(X86CPU *cpu)
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break;
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break;
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case MSR_IA32_FEATURE_CONTROL:
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case MSR_IA32_FEATURE_CONTROL:
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env->msr_ia32_feature_control = msrs[i].data;
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env->msr_ia32_feature_control = msrs[i].data;
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break;
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default:
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default:
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if (msrs[i].index >= MSR_MC0_CTL &&
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if (msrs[i].index >= MSR_MC0_CTL &&
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msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
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msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
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