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target/arm: Remove assert in trans_FCMLA_zzxz 

Since 636ddeb15c, we do not require rd == ra.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-107-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2022-05-27 11:18:59 -07:00 committed by Peter Maydell
parent d961b3e40b
commit df9024760e
1 changed files with 0 additions and 2 deletions
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target/arm/translate-sve.c
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@ -4027,8 +4027,6 @@ static bool trans_FCMLA_zzxz(DisasContext *s, arg_FCMLA_zzxz *a)
NULL,
};
tcg_debug_assert(a->rd == a->ra);
return gen_gvec_fpst_zzzz(s, fns[a->esz], a->rd, a->rn, a->rm, a->ra,
a->index * 4 + a->rot,
a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);