vga: bugfixes for cirrus and virtio-gpu
-----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.22 (GNU/Linux) iQIcBAABAgAGBQJYoWr3AAoJEEy22O7T6HE4DmUQAJxwAof23jsVRa2z+7s/vv7j 0RbrDl0scXQIrG1BWt6woT+23dAb1/k6Z+tHQznKjnAsjRbY0WmvYZ+FMpRWMyzH nlU2+50HpNGl9chst2/j5jghuelnBkl33yCSPVkGvI9BOGmyznL34zPeXU3DgkRC Ef63dba1tHE/NtfDFS8tqJ6qhwxUiWYOIpQ5beiAZfDzHCoILHOHC8Y/tRobouY0 oYir6vX47amBlgPwVKnqImIa0C5jp/k4HNybzvDMza23xCRFd1Ns4J/HMCnEeSML yv1Ji8py/Qy+zYv9CwzTQt28va1ZlSY19zlVF5uuBJZUsV8OHMwwCgTUAcsS20uk IgAqAR0ZF+XzWqCjCQtMwZrG1H77sAMiXB2dq/p2kWP7LCUcSzEe67uUoOipeeQK bo2zt278EQs4ibbiaqFywCdjjedl3cJ31/rlJTXyjjsuv2TPe5Cw3u9dRFFqk413 Hx5MbQyU1IBHyfONeJ0mR28jX23rmOVDxbIKUKPxUpqU2VrbfhtxwizzT0Mg/NPz EyM6CX2UYZdxd7vwDoi+dEU/YugKZXe2DcarmawhUNfzj1LZNhyHdoZU4XYYITKc 4xYn8+EzOx/XXq1NSaG/X9sMwnZG9iJ1cJxzbVX13Vmc5tIqV9eDjHmj/Xu+FbDe TQ127J+jHnXQfz75lWd8 =x7+J -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/kraxel/tags/pull-vga-20170213-1' into staging vga: bugfixes for cirrus and virtio-gpu # gpg: Signature made Mon 13 Feb 2017 08:14:47 GMT # gpg: using RSA key 0x4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/pull-vga-20170213-1: Revert "cirrus: allow zero source pitch in pattern fill rops" cirrus: fix patterncopy checks cirrus: replace debug printf with trace points vga: replace debug printf with trace points virtio-gpu: fix resource leak in virgl_cmd_resource_unref virtio-gpu: fix memory leak in set scanout Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
df96bfab49
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@ -28,6 +28,7 @@
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "trace.h"
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#include "hw/hw.h"
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#include "hw/pci/pci.h"
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#include "ui/console.h"
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@ -272,6 +273,9 @@ static void cirrus_update_memory_access(CirrusVGAState *s);
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static bool blit_region_is_unsafe(struct CirrusVGAState *s,
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int32_t pitch, int32_t addr)
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{
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if (!pitch) {
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return true;
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}
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if (pitch < 0) {
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int64_t min = addr
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+ ((int64_t)s->cirrus_blt_height - 1) * pitch
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@ -290,11 +294,8 @@ static bool blit_region_is_unsafe(struct CirrusVGAState *s,
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return false;
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}
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static bool blit_is_unsafe(struct CirrusVGAState *s, bool dst_only,
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bool zero_src_pitch_ok)
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static bool blit_is_unsafe(struct CirrusVGAState *s, bool dst_only)
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{
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int32_t check_pitch;
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/* should be the case, see cirrus_bitblt_start */
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assert(s->cirrus_blt_width > 0);
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assert(s->cirrus_blt_height > 0);
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@ -303,10 +304,6 @@ static bool blit_is_unsafe(struct CirrusVGAState *s, bool dst_only,
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return true;
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}
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if (!s->cirrus_blt_dstpitch) {
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return true;
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}
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if (blit_region_is_unsafe(s, s->cirrus_blt_dstpitch,
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s->cirrus_blt_dstaddr)) {
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return true;
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@ -314,13 +311,7 @@ static bool blit_is_unsafe(struct CirrusVGAState *s, bool dst_only,
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if (dst_only) {
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return false;
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}
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check_pitch = s->cirrus_blt_srcpitch;
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if (!zero_src_pitch_ok && !check_pitch) {
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check_pitch = s->cirrus_blt_width;
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}
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if (blit_region_is_unsafe(s, check_pitch,
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if (blit_region_is_unsafe(s, s->cirrus_blt_srcpitch,
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s->cirrus_blt_srcaddr)) {
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return true;
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}
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@ -683,14 +674,39 @@ static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
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}
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}
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static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
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const uint8_t * src)
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static int cirrus_bitblt_common_patterncopy(CirrusVGAState *s, bool videosrc)
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{
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uint32_t patternsize;
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uint8_t *dst;
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uint8_t *src;
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dst = s->vga.vram_ptr + s->cirrus_blt_dstaddr;
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if (blit_is_unsafe(s, false, true)) {
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if (videosrc) {
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switch (s->vga.get_bpp(&s->vga)) {
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case 8:
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patternsize = 64;
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break;
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case 15:
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case 16:
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patternsize = 128;
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break;
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case 24:
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case 32:
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default:
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patternsize = 256;
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break;
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}
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s->cirrus_blt_srcaddr &= ~(patternsize - 1);
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if (s->cirrus_blt_srcaddr + patternsize > s->vga.vram_size) {
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return 0;
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}
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src = s->vga.vram_ptr + s->cirrus_blt_srcaddr;
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} else {
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src = s->cirrus_bltbuf;
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}
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if (blit_is_unsafe(s, true)) {
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return 0;
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}
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@ -709,7 +725,7 @@ static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
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{
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cirrus_fill_t rop_func;
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if (blit_is_unsafe(s, true, true)) {
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if (blit_is_unsafe(s, true)) {
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return 0;
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}
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rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
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@ -731,8 +747,7 @@ static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
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static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
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{
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return cirrus_bitblt_common_patterncopy(s, s->vga.vram_ptr +
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(s->cirrus_blt_srcaddr & ~7));
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return cirrus_bitblt_common_patterncopy(s, true);
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}
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static int cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
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@ -810,7 +825,7 @@ static int cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
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static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
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{
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if (blit_is_unsafe(s, false, false))
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if (blit_is_unsafe(s, false))
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return 0;
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return cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->vga.start_addr,
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@ -831,7 +846,7 @@ static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
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if (s->cirrus_srccounter > 0) {
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if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
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cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
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cirrus_bitblt_common_patterncopy(s, false);
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the_end:
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s->cirrus_srccounter = 0;
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cirrus_bitblt_reset(s);
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@ -1852,12 +1867,14 @@ static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
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break;
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}
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trace_vga_cirrus_write_blt(address, value);
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return (uint8_t) value;
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}
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static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
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uint8_t value)
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{
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trace_vga_cirrus_write_blt(address, value);
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switch (address) {
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case (CIRRUS_MMIO_BLTBGCOLOR + 0):
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cirrus_vga_write_gr(s, 0x00, value);
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@ -2607,9 +2624,7 @@ static uint64_t cirrus_vga_ioport_read(void *opaque, hwaddr addr,
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break;
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}
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}
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#if defined(DEBUG_VGA)
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printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
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#endif
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trace_vga_cirrus_read_io(addr, val);
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return val;
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}
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@ -2626,9 +2641,7 @@ static void cirrus_vga_ioport_write(void *opaque, hwaddr addr, uint64_t val,
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if (vga_ioport_invalid(s, addr)) {
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return;
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}
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#ifdef DEBUG_VGA
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printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
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#endif
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trace_vga_cirrus_write_io(addr, val);
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switch (addr) {
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case 0x3c0:
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@ -119,3 +119,15 @@ qxl_set_client_capabilities_unsupported_by_revision(int qid, int revision) "%d r
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qxl_render_blit(int32_t stride, int32_t left, int32_t right, int32_t top, int32_t bottom) "stride=%d [%d, %d, %d, %d]"
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qxl_render_guest_primary_resized(int32_t width, int32_t height, int32_t stride, int32_t bytes_pp, int32_t bits_pp) "%dx%d, stride %d, bpp %d, depth %d"
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qxl_render_update_area_done(void *cookie) "%p"
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# hw/display/vga.c
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vga_std_read_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x"
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vga_std_write_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x"
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vga_vbe_read(uint32_t index, uint32_t val) "index 0x%x, val 0x%x"
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vga_vbe_write(uint32_t index, uint32_t val) "index 0x%x, val 0x%x"
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# hw/display/cirrus_vga.c
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vga_cirrus_read_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x"
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vga_cirrus_write_io(uint32_t addr, uint32_t val) "addr 0x%x, val 0x%x"
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vga_cirrus_read_blt(uint32_t offset, uint32_t val) "offset 0x%x, val 0x%x"
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vga_cirrus_write_blt(uint32_t offset, uint32_t val) "offset 0x%x, val 0x%x"
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@ -34,12 +34,9 @@
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#include "hw/xen/xen.h"
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#include "trace.h"
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//#define DEBUG_VGA
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//#define DEBUG_VGA_MEM
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//#define DEBUG_VGA_REG
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//#define DEBUG_BOCHS_VBE
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/* 16 state changes per vertical frame @60 Hz */
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#define VGA_TEXT_CURSOR_PERIOD_MS (1000 * 2 * 16 / 60)
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@ -428,9 +425,7 @@ uint32_t vga_ioport_read(void *opaque, uint32_t addr)
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break;
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}
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}
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#if defined(DEBUG_VGA)
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printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
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#endif
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trace_vga_std_read_io(addr, val);
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return val;
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}
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@ -443,9 +438,7 @@ void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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if (vga_ioport_invalid(s, addr)) {
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return;
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}
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#ifdef DEBUG_VGA
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printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
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#endif
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trace_vga_std_write_io(addr, val);
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switch(addr) {
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case VGA_ATT_W:
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@ -733,9 +726,7 @@ uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
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} else {
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val = 0;
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}
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#ifdef DEBUG_BOCHS_VBE
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printf("VBE: read index=0x%x val=0x%x\n", s->vbe_index, val);
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#endif
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trace_vga_vbe_read(s->vbe_index, val);
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return val;
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}
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@ -750,9 +741,7 @@ void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
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VGACommonState *s = opaque;
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if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
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#ifdef DEBUG_BOCHS_VBE
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printf("VBE: write index=0x%x val=0x%x\n", s->vbe_index, val);
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#endif
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trace_vga_vbe_write(s->vbe_index, val);
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switch(s->vbe_index) {
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case VBE_DISPI_INDEX_ID:
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if (val == VBE_DISPI_ID0 ||
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@ -1543,17 +1532,9 @@ static void vga_draw_graphic(VGACommonState *s, int full_update)
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height, format, s->line_offset,
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s->vram_ptr + (s->start_addr * 4));
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dpy_gfx_replace_surface(s->con, surface);
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#ifdef DEBUG_VGA
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printf("VGA: Using shared surface for depth=%d swap=%d\n",
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depth, byteswap);
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#endif
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} else {
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qemu_console_resize(s->con, disp_width, height);
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surface = qemu_console_surface(s->con);
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#ifdef DEBUG_VGA
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printf("VGA: Using shadow surface for depth=%d swap=%d\n",
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depth, byteswap);
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#endif
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}
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s->last_scr_width = disp_width;
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s->last_scr_height = height;
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@ -77,10 +77,18 @@ static void virgl_cmd_resource_unref(VirtIOGPU *g,
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struct virtio_gpu_ctrl_command *cmd)
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{
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struct virtio_gpu_resource_unref unref;
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struct iovec *res_iovs = NULL;
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int num_iovs = 0;
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VIRTIO_GPU_FILL_CMD(unref);
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trace_virtio_gpu_cmd_res_unref(unref.resource_id);
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virgl_renderer_resource_detach_iov(unref.resource_id,
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&res_iovs,
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&num_iovs);
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if (res_iovs != NULL && num_iovs != 0) {
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virtio_gpu_cleanup_mapping_iov(res_iovs, num_iovs);
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}
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virgl_renderer_resource_unref(unref.resource_id);
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}
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@ -608,6 +608,7 @@ static void virtio_gpu_set_scanout(VirtIOGPU *g,
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cmd->error = VIRTIO_GPU_RESP_ERR_UNSPEC;
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return;
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}
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pixman_image_unref(rect);
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dpy_gfx_replace_surface(g->scanout[ss.scanout_id].con, scanout->ds);
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}
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