target/arm: Implement Neoverse N2 CPU model
Implement a model of the Neoverse N2 CPU. This is an Armv9.0-A processor very similar to the Cortex-A710. The differences are: * no FEAT_EVT * FEAT_DGH (data gathering hint) * FEAT_NV (not yet implemented in QEMU) * Statistical Profiling Extension (not implemented in QEMU) * 48 bit physical address range, not 40 * CTR_EL0.DIC = 1 (no explicit icache cleaning needed) * PMCR_EL0.N = 6 (always 6 PMU counters, not 20) Because it has 48-bit physical address support, we can use this CPU in the sbsa-ref board as well as the virt board. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20230915185453.1871167-3-peter.maydell@linaro.org
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Peter Maydell
parent
3bcc53980b
commit
dfff1000fe
@ -63,6 +63,7 @@ Supported guest CPU types:
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- ``host`` (with KVM only)
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- ``neoverse-n1`` (64-bit)
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- ``neoverse-v1`` (64-bit)
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- ``neoverse-n2`` (64-bit)
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- ``max`` (same as ``host`` for KVM; best possible emulation with TCG)
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Note that the default is ``cortex-a15``, so for an AArch64 guest you must
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@ -149,6 +149,7 @@ static const char * const valid_cpus[] = {
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ARM_CPU_TYPE_NAME("cortex-a72"),
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ARM_CPU_TYPE_NAME("neoverse-n1"),
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ARM_CPU_TYPE_NAME("neoverse-v1"),
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ARM_CPU_TYPE_NAME("neoverse-n2"),
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ARM_CPU_TYPE_NAME("max"),
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};
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@ -215,6 +215,7 @@ static const char *valid_cpus[] = {
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ARM_CPU_TYPE_NAME("a64fx"),
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ARM_CPU_TYPE_NAME("neoverse-n1"),
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ARM_CPU_TYPE_NAME("neoverse-v1"),
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ARM_CPU_TYPE_NAME("neoverse-n2"),
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#endif
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ARM_CPU_TYPE_NAME("cortex-a53"),
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ARM_CPU_TYPE_NAME("cortex-a57"),
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@ -963,6 +963,108 @@ static void aarch64_a710_initfn(Object *obj)
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aarch64_add_sve_properties(obj);
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}
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/* Extra IMPDEF regs in the N2 beyond those in the A710 */
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static const ARMCPRegInfo neoverse_n2_cp_reginfo[] = {
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{ .name = "CPURNDBR_EL3", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 6, .crn = 15, .crm = 3, .opc2 = 0,
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.access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "CPURNDPEID_EL3", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 6, .crn = 15, .crm = 3, .opc2 = 1,
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.access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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};
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static void aarch64_neoverse_n2_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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cpu->dtb_compatible = "arm,neoverse-n2";
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set_feature(&cpu->env, ARM_FEATURE_V8);
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set_feature(&cpu->env, ARM_FEATURE_NEON);
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set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
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set_feature(&cpu->env, ARM_FEATURE_AARCH64);
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set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
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set_feature(&cpu->env, ARM_FEATURE_EL2);
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set_feature(&cpu->env, ARM_FEATURE_EL3);
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set_feature(&cpu->env, ARM_FEATURE_PMU);
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/* Ordered by Section B.5: AArch64 ID registers */
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cpu->midr = 0x410FD493; /* r0p3 */
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cpu->revidr = 0;
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cpu->isar.id_pfr0 = 0x21110131;
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cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
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cpu->isar.id_dfr0 = 0x16011099;
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cpu->id_afr0 = 0;
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cpu->isar.id_mmfr0 = 0x10201105;
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cpu->isar.id_mmfr1 = 0x40000000;
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cpu->isar.id_mmfr2 = 0x01260000;
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cpu->isar.id_mmfr3 = 0x02122211;
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cpu->isar.id_isar0 = 0x02101110;
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cpu->isar.id_isar1 = 0x13112111;
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cpu->isar.id_isar2 = 0x21232042;
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cpu->isar.id_isar3 = 0x01112131;
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cpu->isar.id_isar4 = 0x00010142;
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cpu->isar.id_isar5 = 0x11011121; /* with Crypto */
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cpu->isar.id_mmfr4 = 0x01021110;
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cpu->isar.id_isar6 = 0x01111111;
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cpu->isar.mvfr0 = 0x10110222;
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cpu->isar.mvfr1 = 0x13211111;
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cpu->isar.mvfr2 = 0x00000043;
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cpu->isar.id_pfr2 = 0x00000011;
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cpu->isar.id_aa64pfr0 = 0x1201111120111112ull; /* GIC filled in later */
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cpu->isar.id_aa64pfr1 = 0x0000000000000221ull;
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cpu->isar.id_aa64zfr0 = 0x0000110100110021ull; /* with Crypto */
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cpu->isar.id_aa64dfr0 = 0x000011f210305619ull;
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cpu->isar.id_aa64dfr1 = 0;
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cpu->id_aa64afr0 = 0;
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cpu->id_aa64afr1 = 0;
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cpu->isar.id_aa64isar0 = 0x0221111110212120ull; /* with Crypto */
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cpu->isar.id_aa64isar1 = 0x0011111101211052ull;
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cpu->isar.id_aa64mmfr0 = 0x0000022200101125ull;
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cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
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cpu->isar.id_aa64mmfr2 = 0x1221011112101011ull;
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cpu->clidr = 0x0000001482000023ull;
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cpu->gm_blocksize = 4;
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cpu->ctr = 0x00000004b444c004ull;
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cpu->dcz_blocksize = 4;
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/* TODO FEAT_MPAM: mpamidr_el1 = 0x0000_0001_001e_01ff */
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/* Section B.7.2: PMCR_EL0 */
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cpu->isar.reset_pmcr_el0 = 0x3000; /* with 6 counters */
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/* Section B.8.9: ICH_VTR_EL2 */
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cpu->gic_num_lrs = 4;
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cpu->gic_vpribits = 5;
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cpu->gic_vprebits = 5;
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cpu->gic_pribits = 5;
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/* Section 14: Scalable Vector Extensions support */
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cpu->sve_vq.supported = 1 << 0; /* 128bit */
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/*
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* The Neoverse N2 TRM does not list CCSIDR values. The layout of
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* the caches are in text in Table 7-1, Table 8-1, and Table 9-1.
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*
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* L1: 4-way set associative 64-byte line size, total 64K.
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* L2: 8-way set associative 64 byte line size, total either 512K or 1024K.
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*/
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cpu->ccsidr[0] = make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */
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cpu->ccsidr[1] = cpu->ccsidr[0]; /* L1 icache */
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cpu->ccsidr[2] = make_ccsidr64(8, 64, 512 * KiB); /* L2 cache */
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/* FIXME: Not documented -- copied from neoverse-v1 */
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cpu->reset_sctlr = 0x30c50838;
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/*
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* The Neoverse N2 has all of the Cortex-A710 IMPDEF registers,
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* and a few more RNG related ones.
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*/
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define_arm_cp_regs(cpu, cortex_a710_cp_reginfo);
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define_arm_cp_regs(cpu, neoverse_n2_cp_reginfo);
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aarch64_add_pauth_properties(obj);
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aarch64_add_sve_properties(obj);
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}
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/*
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* -cpu max: a CPU with as many features enabled as our emulation supports.
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* The version of '-cpu max' for qemu-system-arm is defined in cpu32.c;
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@ -1165,6 +1267,7 @@ static const ARMCPUInfo aarch64_cpus[] = {
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{ .name = "a64fx", .initfn = aarch64_a64fx_initfn },
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{ .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn },
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{ .name = "neoverse-v1", .initfn = aarch64_neoverse_v1_initfn },
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{ .name = "neoverse-n2", .initfn = aarch64_neoverse_n2_initfn },
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};
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static void aarch64_cpu_register_types(void)
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