tcg-aarch64: Handle constant operands to and, or, xor
Handle a simplified set of logical immediates for the moment. The way gcc and binutils do it, with 52k worth of tables, and a binary search depth of log2(5334) = 13, seems slow for the most common cases. Signed-off-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com> Tested-by: Claudio Fontana <claudio.fontana@huawei.com>
This commit is contained in:
Richard Henderson
parent
90f1cd9138
commit
e029f29385
@ -112,6 +112,7 @@ static inline void patch_reloc(uint8_t *code_ptr, int type,
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#define TCG_CT_CONST_IS32 0x100
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#define TCG_CT_CONST_AIMM 0x200
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#define TCG_CT_CONST_LIMM 0x400
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/* parse target specific constraints */
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static int target_parse_constraint(TCGArgConstraint *ct,
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@ -142,6 +143,9 @@ static int target_parse_constraint(TCGArgConstraint *ct,
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case 'A': /* Valid for arithmetic immediate (positive or negative). */
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ct->ct |= TCG_CT_CONST_AIMM;
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break;
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case 'L': /* Valid for logical immediate. */
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ct->ct |= TCG_CT_CONST_LIMM;
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break;
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default:
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return -1;
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}
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@ -156,6 +160,26 @@ static inline bool is_aimm(uint64_t val)
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return (val & ~0xfff) == 0 || (val & ~0xfff000) == 0;
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}
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static inline bool is_limm(uint64_t val)
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{
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/* Taking a simplified view of the logical immediates for now, ignoring
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the replication that can happen across the field. Match bit patterns
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of the forms
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0....01....1
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0..01..10..0
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and their inverses. */
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/* Make things easier below, by testing the form with msb clear. */
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if ((int64_t)val < 0) {
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val = ~val;
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}
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if (val == 0) {
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return false;
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}
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val += val & -val;
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return (val & (val - 1)) == 0;
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}
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static int tcg_target_const_match(tcg_target_long val,
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const TCGArgConstraint *arg_ct)
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{
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@ -170,6 +194,9 @@ static int tcg_target_const_match(tcg_target_long val,
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if ((ct & TCG_CT_CONST_AIMM) && (is_aimm(val) || is_aimm(-val))) {
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return 1;
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}
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if ((ct & TCG_CT_CONST_LIMM) && is_limm(val)) {
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return 1;
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}
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return 0;
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}
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@ -235,6 +262,11 @@ typedef enum {
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I3401_SUBI = 0x51000000,
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I3401_SUBSI = 0x71000000,
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/* Logical immediate instructions. */
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I3404_ANDI = 0x12000000,
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I3404_ORRI = 0x32000000,
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I3404_EORI = 0x52000000,
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/* Add/subtract shifted register instructions (without a shift). */
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I3502_ADD = 0x0b000000,
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I3502_ADDS = 0x2b000000,
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@ -351,6 +383,18 @@ static void tcg_out_insn_3401(TCGContext *s, AArch64Insn insn, TCGType ext,
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tcg_out32(s, insn | ext << 31 | aimm << 10 | rn << 5 | rd);
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}
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/* This function can be used for both 3.4.2 (Bitfield) and 3.4.4
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(Logical immediate). Both insn groups have N, IMMR and IMMS fields
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that feed the DecodeBitMasks pseudo function. */
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static void tcg_out_insn_3402(TCGContext *s, AArch64Insn insn, TCGType ext,
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TCGReg rd, TCGReg rn, int n, int immr, int imms)
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{
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tcg_out32(s, insn | ext << 31 | n << 22 | immr << 16 | imms << 10
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| rn << 5 | rd);
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}
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#define tcg_out_insn_3404 tcg_out_insn_3402
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/* This function is for both 3.5.2 (Add/Subtract shifted register), for
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the rare occasion when we actually want to supply a shift amount. */
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static inline void tcg_out_insn_3502S(TCGContext *s, AArch64Insn insn,
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@ -665,40 +709,6 @@ static inline void tcg_out_call(TCGContext *s, intptr_t target)
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}
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}
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/* encode a logical immediate, mapping user parameter
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M=set bits pattern length to S=M-1 */
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static inline unsigned int
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aarch64_limm(unsigned int m, unsigned int r)
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{
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assert(m > 0);
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return r << 16 | (m - 1) << 10;
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}
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/* test a register against an immediate bit pattern made of
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M set bits rotated right by R.
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Examples:
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to test a 32/64 reg against 0x00000007, pass M = 3, R = 0.
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to test a 32/64 reg against 0x000000ff, pass M = 8, R = 0.
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to test a 32bit reg against 0xff000000, pass M = 8, R = 8.
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to test a 32bit reg against 0xff0000ff, pass M = 16, R = 8.
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*/
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static inline void tcg_out_tst(TCGContext *s, TCGType ext, TCGReg rn,
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unsigned int m, unsigned int r)
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{
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/* using TST alias of ANDS XZR, Xn,#bimm64 0x7200001f */
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unsigned int base = ext ? 0xf240001f : 0x7200001f;
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tcg_out32(s, base | aarch64_limm(m, r) | rn << 5);
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}
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/* and a register with a bit pattern, similarly to TST, no flags change */
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static inline void tcg_out_andi(TCGContext *s, TCGType ext, TCGReg rd,
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TCGReg rn, unsigned int m, unsigned int r)
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{
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/* using AND 0x12000000 */
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unsigned int base = ext ? 0x92400000 : 0x12000000;
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tcg_out32(s, base | aarch64_limm(m, r) | rn << 5 | rd);
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}
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static inline void tcg_out_ret(TCGContext *s)
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{
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/* emit RET { LR } */
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@ -788,6 +798,37 @@ static void tcg_out_addsubi(TCGContext *s, int ext, TCGReg rd,
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}
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}
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/* This function is used for the Logical (immediate) instruction group.
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The value of LIMM must satisfy IS_LIMM. See the comment above about
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only supporting simplified logical immediates. */
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static void tcg_out_logicali(TCGContext *s, AArch64Insn insn, TCGType ext,
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TCGReg rd, TCGReg rn, uint64_t limm)
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{
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unsigned h, l, r, c;
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assert(is_limm(limm));
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h = clz64(limm);
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l = ctz64(limm);
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if (l == 0) {
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r = 0; /* form 0....01....1 */
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c = ctz64(~limm) - 1;
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if (h == 0) {
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r = clz64(~limm); /* form 1..10..01..1 */
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c += r;
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}
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} else {
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r = 64 - l; /* form 1....10....0 or 0..01..10..0 */
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c = r - h - 1;
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}
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if (ext == TCG_TYPE_I32) {
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r &= 31;
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c &= 31;
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}
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tcg_out_insn_3404(s, insn, ext, rd, rn, ext, r, c);
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}
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#ifdef CONFIG_SOFTMMU
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/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
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* int mmu_idx, uintptr_t ra)
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@ -879,9 +920,8 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg,
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/* Store the page mask part of the address and the low s_bits into X3.
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Later this allows checking for equality and alignment at the same time.
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X3 = addr_reg & (PAGE_MASK | ((1 << s_bits) - 1)) */
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tcg_out_andi(s, (TARGET_LONG_BITS == 64), TCG_REG_X3, addr_reg,
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(TARGET_LONG_BITS - TARGET_PAGE_BITS) + s_bits,
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(TARGET_LONG_BITS - TARGET_PAGE_BITS));
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tcg_out_logicali(s, I3404_ANDI, TARGET_LONG_BITS == 64, TCG_REG_X3,
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addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
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/* Add any "high bits" from the tlb offset to the env address into X2,
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to take advantage of the LSL12 form of the ADDI instruction.
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X2 = env + (tlb_offset & 0xfff000) */
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@ -1186,19 +1226,37 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
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}
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break;
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case INDEX_op_and_i64:
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case INDEX_op_and_i32:
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tcg_out_insn(s, 3510, AND, ext, a0, a1, a2);
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a2 = (int32_t)a2;
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/* FALLTHRU */
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case INDEX_op_and_i64:
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if (c2) {
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tcg_out_logicali(s, I3404_ANDI, ext, a0, a1, a2);
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} else {
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tcg_out_insn(s, 3510, AND, ext, a0, a1, a2);
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}
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break;
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case INDEX_op_or_i64:
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case INDEX_op_or_i32:
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tcg_out_insn(s, 3510, ORR, ext, a0, a1, a2);
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a2 = (int32_t)a2;
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/* FALLTHRU */
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case INDEX_op_or_i64:
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if (c2) {
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tcg_out_logicali(s, I3404_ORRI, ext, a0, a1, a2);
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} else {
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tcg_out_insn(s, 3510, ORR, ext, a0, a1, a2);
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}
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break;
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case INDEX_op_xor_i64:
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case INDEX_op_xor_i32:
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tcg_out_insn(s, 3510, EOR, ext, a0, a1, a2);
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a2 = (int32_t)a2;
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/* FALLTHRU */
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case INDEX_op_xor_i64:
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if (c2) {
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tcg_out_logicali(s, I3404_EORI, ext, a0, a1, a2);
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} else {
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tcg_out_insn(s, 3510, EOR, ext, a0, a1, a2);
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}
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break;
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case INDEX_op_mul_i64:
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@ -1391,12 +1449,12 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
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{ INDEX_op_sub_i64, { "r", "r", "rA" } },
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{ INDEX_op_mul_i32, { "r", "r", "r" } },
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{ INDEX_op_mul_i64, { "r", "r", "r" } },
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{ INDEX_op_and_i32, { "r", "r", "r" } },
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{ INDEX_op_and_i64, { "r", "r", "r" } },
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{ INDEX_op_or_i32, { "r", "r", "r" } },
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{ INDEX_op_or_i64, { "r", "r", "r" } },
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{ INDEX_op_xor_i32, { "r", "r", "r" } },
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{ INDEX_op_xor_i64, { "r", "r", "r" } },
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{ INDEX_op_and_i32, { "r", "r", "rwL" } },
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{ INDEX_op_and_i64, { "r", "r", "rL" } },
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{ INDEX_op_or_i32, { "r", "r", "rwL" } },
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{ INDEX_op_or_i64, { "r", "r", "rL" } },
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{ INDEX_op_xor_i32, { "r", "r", "rwL" } },
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{ INDEX_op_xor_i64, { "r", "r", "rL" } },
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{ INDEX_op_shl_i32, { "r", "r", "ri" } },
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{ INDEX_op_shr_i32, { "r", "r", "ri" } },
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