target/arm: Move arm_gen_dynamic_svereg_xml to gdbstub64.c
The function is only used for aarch64, so move it to the file that has the other aarch64 gdbstub stuff. Move the declaration to internals.h. Reviewed-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230227213329.793795-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
4bce95b45e
commit
e03aba8853
|
|
@ -1112,12 +1112,6 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
|
|||
int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
|
||||
int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
|
||||
|
||||
/*
|
||||
* Helpers to dynamically generates XML descriptions of the sysregs
|
||||
* and SVE registers. Returns the number of registers in each set.
|
||||
*/
|
||||
int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
|
||||
|
||||
/* Returns the dynamically generated XML for the gdb stub.
|
||||
* Returns a pointer to the XML contents for the specified XML file or NULL
|
||||
* if the XML name doesn't match the predefined one.
|
||||
|
|
|
|||
|
|
@ -322,126 +322,6 @@ static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
|
|||
return cpu->dyn_sysreg_xml.num;
|
||||
}
|
||||
|
||||
struct TypeSize {
|
||||
const char *gdb_type;
|
||||
int size;
|
||||
const char sz, suffix;
|
||||
};
|
||||
|
||||
static const struct TypeSize vec_lanes[] = {
|
||||
/* quads */
|
||||
{ "uint128", 128, 'q', 'u' },
|
||||
{ "int128", 128, 'q', 's' },
|
||||
/* 64 bit */
|
||||
{ "ieee_double", 64, 'd', 'f' },
|
||||
{ "uint64", 64, 'd', 'u' },
|
||||
{ "int64", 64, 'd', 's' },
|
||||
/* 32 bit */
|
||||
{ "ieee_single", 32, 's', 'f' },
|
||||
{ "uint32", 32, 's', 'u' },
|
||||
{ "int32", 32, 's', 's' },
|
||||
/* 16 bit */
|
||||
{ "ieee_half", 16, 'h', 'f' },
|
||||
{ "uint16", 16, 'h', 'u' },
|
||||
{ "int16", 16, 'h', 's' },
|
||||
/* bytes */
|
||||
{ "uint8", 8, 'b', 'u' },
|
||||
{ "int8", 8, 'b', 's' },
|
||||
};
|
||||
|
||||
|
||||
int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
|
||||
{
|
||||
ARMCPU *cpu = ARM_CPU(cs);
|
||||
GString *s = g_string_new(NULL);
|
||||
DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
|
||||
g_autoptr(GString) ts = g_string_new("");
|
||||
int i, j, bits, reg_width = (cpu->sve_max_vq * 128);
|
||||
info->num = 0;
|
||||
g_string_printf(s, "<?xml version=\"1.0\"?>");
|
||||
g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
|
||||
g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
|
||||
|
||||
/* First define types and totals in a whole VL */
|
||||
for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
|
||||
int count = reg_width / vec_lanes[i].size;
|
||||
g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix);
|
||||
g_string_append_printf(s,
|
||||
"<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
|
||||
ts->str, vec_lanes[i].gdb_type, count);
|
||||
}
|
||||
/*
|
||||
* Now define a union for each size group containing unsigned and
|
||||
* signed and potentially float versions of each size from 128 to
|
||||
* 8 bits.
|
||||
*/
|
||||
for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
|
||||
const char suf[] = { 'q', 'd', 's', 'h', 'b' };
|
||||
g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
|
||||
for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
|
||||
if (vec_lanes[j].size == bits) {
|
||||
g_string_append_printf(s, "<field name=\"%c\" type=\"svev%c%c\"/>",
|
||||
vec_lanes[j].suffix,
|
||||
vec_lanes[j].sz, vec_lanes[j].suffix);
|
||||
}
|
||||
}
|
||||
g_string_append(s, "</union>");
|
||||
}
|
||||
/* And now the final union of unions */
|
||||
g_string_append(s, "<union id=\"svev\">");
|
||||
for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
|
||||
const char suf[] = { 'q', 'd', 's', 'h', 'b' };
|
||||
g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
|
||||
suf[i], suf[i]);
|
||||
}
|
||||
g_string_append(s, "</union>");
|
||||
|
||||
/* Finally the sve prefix type */
|
||||
g_string_append_printf(s,
|
||||
"<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
|
||||
reg_width / 8);
|
||||
|
||||
/* Then define each register in parts for each vq */
|
||||
for (i = 0; i < 32; i++) {
|
||||
g_string_append_printf(s,
|
||||
"<reg name=\"z%d\" bitsize=\"%d\""
|
||||
" regnum=\"%d\" type=\"svev\"/>",
|
||||
i, reg_width, base_reg++);
|
||||
info->num++;
|
||||
}
|
||||
/* fpscr & status registers */
|
||||
g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
|
||||
" regnum=\"%d\" group=\"float\""
|
||||
" type=\"int\"/>", base_reg++);
|
||||
g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
|
||||
" regnum=\"%d\" group=\"float\""
|
||||
" type=\"int\"/>", base_reg++);
|
||||
info->num += 2;
|
||||
|
||||
for (i = 0; i < 16; i++) {
|
||||
g_string_append_printf(s,
|
||||
"<reg name=\"p%d\" bitsize=\"%d\""
|
||||
" regnum=\"%d\" type=\"svep\"/>",
|
||||
i, cpu->sve_max_vq * 16, base_reg++);
|
||||
info->num++;
|
||||
}
|
||||
g_string_append_printf(s,
|
||||
"<reg name=\"ffr\" bitsize=\"%d\""
|
||||
" regnum=\"%d\" group=\"vector\""
|
||||
" type=\"svep\"/>",
|
||||
cpu->sve_max_vq * 16, base_reg++);
|
||||
g_string_append_printf(s,
|
||||
"<reg name=\"vg\" bitsize=\"64\""
|
||||
" regnum=\"%d\" type=\"int\"/>",
|
||||
base_reg++);
|
||||
info->num += 2;
|
||||
g_string_append_printf(s, "</feature>");
|
||||
cpu->dyn_svereg_xml.desc = g_string_free(s, false);
|
||||
|
||||
return cpu->dyn_svereg_xml.num;
|
||||
}
|
||||
|
||||
|
||||
const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
|
||||
{
|
||||
ARMCPU *cpu = ARM_CPU(cs);
|
||||
|
|
|
|||
|
|
@ -209,3 +209,121 @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
|
|||
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct TypeSize {
|
||||
const char *gdb_type;
|
||||
short size;
|
||||
char sz, suffix;
|
||||
};
|
||||
|
||||
static const struct TypeSize vec_lanes[] = {
|
||||
/* quads */
|
||||
{ "uint128", 128, 'q', 'u' },
|
||||
{ "int128", 128, 'q', 's' },
|
||||
/* 64 bit */
|
||||
{ "ieee_double", 64, 'd', 'f' },
|
||||
{ "uint64", 64, 'd', 'u' },
|
||||
{ "int64", 64, 'd', 's' },
|
||||
/* 32 bit */
|
||||
{ "ieee_single", 32, 's', 'f' },
|
||||
{ "uint32", 32, 's', 'u' },
|
||||
{ "int32", 32, 's', 's' },
|
||||
/* 16 bit */
|
||||
{ "ieee_half", 16, 'h', 'f' },
|
||||
{ "uint16", 16, 'h', 'u' },
|
||||
{ "int16", 16, 'h', 's' },
|
||||
/* bytes */
|
||||
{ "uint8", 8, 'b', 'u' },
|
||||
{ "int8", 8, 'b', 's' },
|
||||
};
|
||||
|
||||
int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
|
||||
{
|
||||
ARMCPU *cpu = ARM_CPU(cs);
|
||||
GString *s = g_string_new(NULL);
|
||||
DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
|
||||
g_autoptr(GString) ts = g_string_new("");
|
||||
int i, j, bits, reg_width = (cpu->sve_max_vq * 128);
|
||||
info->num = 0;
|
||||
g_string_printf(s, "<?xml version=\"1.0\"?>");
|
||||
g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
|
||||
g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
|
||||
|
||||
/* First define types and totals in a whole VL */
|
||||
for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
|
||||
int count = reg_width / vec_lanes[i].size;
|
||||
g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix);
|
||||
g_string_append_printf(s,
|
||||
"<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
|
||||
ts->str, vec_lanes[i].gdb_type, count);
|
||||
}
|
||||
/*
|
||||
* Now define a union for each size group containing unsigned and
|
||||
* signed and potentially float versions of each size from 128 to
|
||||
* 8 bits.
|
||||
*/
|
||||
for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
|
||||
const char suf[] = { 'q', 'd', 's', 'h', 'b' };
|
||||
g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
|
||||
for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
|
||||
if (vec_lanes[j].size == bits) {
|
||||
g_string_append_printf(s, "<field name=\"%c\" type=\"svev%c%c\"/>",
|
||||
vec_lanes[j].suffix,
|
||||
vec_lanes[j].sz, vec_lanes[j].suffix);
|
||||
}
|
||||
}
|
||||
g_string_append(s, "</union>");
|
||||
}
|
||||
/* And now the final union of unions */
|
||||
g_string_append(s, "<union id=\"svev\">");
|
||||
for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
|
||||
const char suf[] = { 'q', 'd', 's', 'h', 'b' };
|
||||
g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
|
||||
suf[i], suf[i]);
|
||||
}
|
||||
g_string_append(s, "</union>");
|
||||
|
||||
/* Finally the sve prefix type */
|
||||
g_string_append_printf(s,
|
||||
"<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
|
||||
reg_width / 8);
|
||||
|
||||
/* Then define each register in parts for each vq */
|
||||
for (i = 0; i < 32; i++) {
|
||||
g_string_append_printf(s,
|
||||
"<reg name=\"z%d\" bitsize=\"%d\""
|
||||
" regnum=\"%d\" type=\"svev\"/>",
|
||||
i, reg_width, base_reg++);
|
||||
info->num++;
|
||||
}
|
||||
/* fpscr & status registers */
|
||||
g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
|
||||
" regnum=\"%d\" group=\"float\""
|
||||
" type=\"int\"/>", base_reg++);
|
||||
g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
|
||||
" regnum=\"%d\" group=\"float\""
|
||||
" type=\"int\"/>", base_reg++);
|
||||
info->num += 2;
|
||||
|
||||
for (i = 0; i < 16; i++) {
|
||||
g_string_append_printf(s,
|
||||
"<reg name=\"p%d\" bitsize=\"%d\""
|
||||
" regnum=\"%d\" type=\"svep\"/>",
|
||||
i, cpu->sve_max_vq * 16, base_reg++);
|
||||
info->num++;
|
||||
}
|
||||
g_string_append_printf(s,
|
||||
"<reg name=\"ffr\" bitsize=\"%d\""
|
||||
" regnum=\"%d\" group=\"vector\""
|
||||
" type=\"svep\"/>",
|
||||
cpu->sve_max_vq * 16, base_reg++);
|
||||
g_string_append_printf(s,
|
||||
"<reg name=\"vg\" bitsize=\"64\""
|
||||
" regnum=\"%d\" type=\"int\"/>",
|
||||
base_reg++);
|
||||
info->num += 2;
|
||||
g_string_append_printf(s, "</feature>");
|
||||
info->desc = g_string_free(s, false);
|
||||
|
||||
return info->num;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1344,6 +1344,7 @@ static inline uint64_t pmu_counter_mask(CPUARMState *env)
|
|||
}
|
||||
|
||||
#ifdef TARGET_AARCH64
|
||||
int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
|
||||
int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg);
|
||||
int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg);
|
||||
int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg);
|
||||
|
|
|
|||
Loading…
Reference in New Issue