target/arm: Move arm_gen_dynamic_svereg_xml to gdbstub64.c
The function is only used for aarch64, so move it to the file that has the other aarch64 gdbstub stuff. Move the declaration to internals.h. Reviewed-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230227213329.793795-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
4bce95b45e
commit
e03aba8853
@ -1112,12 +1112,6 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
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int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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/*
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* Helpers to dynamically generates XML descriptions of the sysregs
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* and SVE registers. Returns the number of registers in each set.
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*/
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int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
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/* Returns the dynamically generated XML for the gdb stub.
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* Returns a pointer to the XML contents for the specified XML file or NULL
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* if the XML name doesn't match the predefined one.
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@ -322,126 +322,6 @@ static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
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return cpu->dyn_sysreg_xml.num;
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}
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struct TypeSize {
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const char *gdb_type;
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int size;
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const char sz, suffix;
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};
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static const struct TypeSize vec_lanes[] = {
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/* quads */
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{ "uint128", 128, 'q', 'u' },
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{ "int128", 128, 'q', 's' },
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/* 64 bit */
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{ "ieee_double", 64, 'd', 'f' },
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{ "uint64", 64, 'd', 'u' },
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{ "int64", 64, 'd', 's' },
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/* 32 bit */
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{ "ieee_single", 32, 's', 'f' },
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{ "uint32", 32, 's', 'u' },
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{ "int32", 32, 's', 's' },
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/* 16 bit */
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{ "ieee_half", 16, 'h', 'f' },
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{ "uint16", 16, 'h', 'u' },
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{ "int16", 16, 'h', 's' },
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/* bytes */
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{ "uint8", 8, 'b', 'u' },
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{ "int8", 8, 'b', 's' },
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};
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int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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GString *s = g_string_new(NULL);
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DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
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g_autoptr(GString) ts = g_string_new("");
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int i, j, bits, reg_width = (cpu->sve_max_vq * 128);
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info->num = 0;
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g_string_printf(s, "<?xml version=\"1.0\"?>");
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g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
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g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
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/* First define types and totals in a whole VL */
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for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
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int count = reg_width / vec_lanes[i].size;
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g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix);
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g_string_append_printf(s,
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"<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
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ts->str, vec_lanes[i].gdb_type, count);
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}
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/*
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* Now define a union for each size group containing unsigned and
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* signed and potentially float versions of each size from 128 to
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* 8 bits.
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*/
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for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
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const char suf[] = { 'q', 'd', 's', 'h', 'b' };
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g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
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for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
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if (vec_lanes[j].size == bits) {
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g_string_append_printf(s, "<field name=\"%c\" type=\"svev%c%c\"/>",
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vec_lanes[j].suffix,
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vec_lanes[j].sz, vec_lanes[j].suffix);
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}
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}
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g_string_append(s, "</union>");
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}
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/* And now the final union of unions */
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g_string_append(s, "<union id=\"svev\">");
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for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
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const char suf[] = { 'q', 'd', 's', 'h', 'b' };
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g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
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suf[i], suf[i]);
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}
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g_string_append(s, "</union>");
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/* Finally the sve prefix type */
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g_string_append_printf(s,
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"<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
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reg_width / 8);
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/* Then define each register in parts for each vq */
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for (i = 0; i < 32; i++) {
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g_string_append_printf(s,
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"<reg name=\"z%d\" bitsize=\"%d\""
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" regnum=\"%d\" type=\"svev\"/>",
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i, reg_width, base_reg++);
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info->num++;
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}
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/* fpscr & status registers */
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g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
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" regnum=\"%d\" group=\"float\""
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" type=\"int\"/>", base_reg++);
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g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
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" regnum=\"%d\" group=\"float\""
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" type=\"int\"/>", base_reg++);
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info->num += 2;
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for (i = 0; i < 16; i++) {
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g_string_append_printf(s,
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"<reg name=\"p%d\" bitsize=\"%d\""
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" regnum=\"%d\" type=\"svep\"/>",
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i, cpu->sve_max_vq * 16, base_reg++);
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info->num++;
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}
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g_string_append_printf(s,
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"<reg name=\"ffr\" bitsize=\"%d\""
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" regnum=\"%d\" group=\"vector\""
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" type=\"svep\"/>",
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cpu->sve_max_vq * 16, base_reg++);
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g_string_append_printf(s,
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"<reg name=\"vg\" bitsize=\"64\""
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" regnum=\"%d\" type=\"int\"/>",
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base_reg++);
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info->num += 2;
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g_string_append_printf(s, "</feature>");
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cpu->dyn_svereg_xml.desc = g_string_free(s, false);
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return cpu->dyn_svereg_xml.num;
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}
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const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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@ -209,3 +209,121 @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)
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return 0;
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}
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struct TypeSize {
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const char *gdb_type;
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short size;
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char sz, suffix;
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};
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static const struct TypeSize vec_lanes[] = {
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/* quads */
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{ "uint128", 128, 'q', 'u' },
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{ "int128", 128, 'q', 's' },
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/* 64 bit */
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{ "ieee_double", 64, 'd', 'f' },
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{ "uint64", 64, 'd', 'u' },
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{ "int64", 64, 'd', 's' },
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/* 32 bit */
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{ "ieee_single", 32, 's', 'f' },
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{ "uint32", 32, 's', 'u' },
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{ "int32", 32, 's', 's' },
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/* 16 bit */
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{ "ieee_half", 16, 'h', 'f' },
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{ "uint16", 16, 'h', 'u' },
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{ "int16", 16, 'h', 's' },
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/* bytes */
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{ "uint8", 8, 'b', 'u' },
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{ "int8", 8, 'b', 's' },
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};
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int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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GString *s = g_string_new(NULL);
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DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
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g_autoptr(GString) ts = g_string_new("");
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int i, j, bits, reg_width = (cpu->sve_max_vq * 128);
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info->num = 0;
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g_string_printf(s, "<?xml version=\"1.0\"?>");
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g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
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g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");
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/* First define types and totals in a whole VL */
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for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
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int count = reg_width / vec_lanes[i].size;
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g_string_printf(ts, "svev%c%c", vec_lanes[i].sz, vec_lanes[i].suffix);
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g_string_append_printf(s,
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"<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
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ts->str, vec_lanes[i].gdb_type, count);
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}
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/*
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* Now define a union for each size group containing unsigned and
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* signed and potentially float versions of each size from 128 to
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* 8 bits.
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*/
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for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
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const char suf[] = { 'q', 'd', 's', 'h', 'b' };
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g_string_append_printf(s, "<union id=\"svevn%c\">", suf[i]);
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for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
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if (vec_lanes[j].size == bits) {
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g_string_append_printf(s, "<field name=\"%c\" type=\"svev%c%c\"/>",
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vec_lanes[j].suffix,
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vec_lanes[j].sz, vec_lanes[j].suffix);
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}
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}
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g_string_append(s, "</union>");
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}
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/* And now the final union of unions */
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g_string_append(s, "<union id=\"svev\">");
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for (bits = 128, i = 0; bits >= 8; bits /= 2, i++) {
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const char suf[] = { 'q', 'd', 's', 'h', 'b' };
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g_string_append_printf(s, "<field name=\"%c\" type=\"svevn%c\"/>",
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suf[i], suf[i]);
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}
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g_string_append(s, "</union>");
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/* Finally the sve prefix type */
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g_string_append_printf(s,
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"<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
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reg_width / 8);
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/* Then define each register in parts for each vq */
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for (i = 0; i < 32; i++) {
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g_string_append_printf(s,
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"<reg name=\"z%d\" bitsize=\"%d\""
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" regnum=\"%d\" type=\"svev\"/>",
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i, reg_width, base_reg++);
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info->num++;
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}
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/* fpscr & status registers */
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g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
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" regnum=\"%d\" group=\"float\""
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" type=\"int\"/>", base_reg++);
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g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
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" regnum=\"%d\" group=\"float\""
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" type=\"int\"/>", base_reg++);
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info->num += 2;
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for (i = 0; i < 16; i++) {
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g_string_append_printf(s,
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"<reg name=\"p%d\" bitsize=\"%d\""
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" regnum=\"%d\" type=\"svep\"/>",
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i, cpu->sve_max_vq * 16, base_reg++);
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info->num++;
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}
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g_string_append_printf(s,
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"<reg name=\"ffr\" bitsize=\"%d\""
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" regnum=\"%d\" group=\"vector\""
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" type=\"svep\"/>",
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cpu->sve_max_vq * 16, base_reg++);
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g_string_append_printf(s,
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"<reg name=\"vg\" bitsize=\"64\""
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" regnum=\"%d\" type=\"int\"/>",
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base_reg++);
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info->num += 2;
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g_string_append_printf(s, "</feature>");
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info->desc = g_string_free(s, false);
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return info->num;
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}
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@ -1344,6 +1344,7 @@ static inline uint64_t pmu_counter_mask(CPUARMState *env)
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}
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#ifdef TARGET_AARCH64
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int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
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int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg);
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int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg);
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int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg);
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