target/riscv: implement Zicbom extension
Zicbom is the Cache-Block Management extension defined in the already ratified RISC-V Base Cache Management Operation (CBO) ISA extension [1]. The extension contains three instructions: cbo.clean, cbo.flush and cbo.inval. All of them must be implemented in the same group as LQ and cbo.zero due to overlapping patterns. All these instructions can throw a Illegal Instruction/Virtual Instruction exception, similar to the existing cbo.zero. The same check_zicbo_envcfg() is used to handle these exceptions. Aside from that, these instructions also need to handle page faults and guest page faults. This is done in a new check_zicbom_access() helper. As with Zicboz, the cache block size for Zicbom is also configurable. Note that the spec determines that Zicbo[mp] and Zicboz can have different cache sizes (Section 2.7 of [1]), so we also include a 'cbom_blocksize' to go along with the existing 'cboz_blocksize'. They are set to the same size, so unless users want to play around with the settings both sizes will be the same. [1] https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0.1.pdf Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Signed-off-by: Christoph Muellner <cmuellner@linux.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230224132536.552293-4-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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@ -75,6 +75,7 @@ struct isa_ext_data {
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static const struct isa_ext_data isa_edata_arr[] = {
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ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h),
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ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_10_0, ext_v),
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ISA_EXT_DATA_ENTRY(zicbom, true, PRIV_VERSION_1_12_0, ext_icbom),
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ISA_EXT_DATA_ENTRY(zicboz, true, PRIV_VERSION_1_12_0, ext_icboz),
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ISA_EXT_DATA_ENTRY(zicond, true, PRIV_VERSION_1_12_0, ext_zicond),
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ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr),
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@ -1168,6 +1169,8 @@ static Property riscv_cpu_extensions[] = {
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DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false),
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DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false),
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DEFINE_PROP_BOOL("zicbom", RISCVCPU, cfg.ext_icbom, true),
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DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64),
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DEFINE_PROP_BOOL("zicboz", RISCVCPU, cfg.ext_icboz, true),
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DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64),
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@ -434,6 +434,7 @@ struct RISCVCPUConfig {
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bool ext_zkt;
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bool ext_ifencei;
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bool ext_icsr;
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bool ext_icbom;
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bool ext_icboz;
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bool ext_zicond;
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bool ext_zihintpause;
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@ -487,6 +488,7 @@ struct RISCVCPUConfig {
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char *vext_spec;
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uint16_t vlen;
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uint16_t elen;
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uint16_t cbom_blocksize;
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uint16_t cboz_blocksize;
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bool mmu;
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bool pmp;
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@ -98,6 +98,8 @@ DEF_HELPER_FLAGS_2(fcvt_h_lu, TCG_CALL_NO_RWG, i64, env, tl)
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DEF_HELPER_FLAGS_2(fclass_h, TCG_CALL_NO_RWG_SE, tl, env, i64)
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/* Cache-block operations */
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DEF_HELPER_2(cbo_clean_flush, void, env, tl)
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DEF_HELPER_2(cbo_inval, void, env, tl)
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DEF_HELPER_2(cbo_zero, void, env, tl)
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/* Special functions */
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@ -181,6 +181,11 @@ sraw 0100000 ..... ..... 101 ..... 0111011 @r
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ldu ............ ..... 111 ..... 0000011 @i
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{
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[
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# *** RV32 Zicbom Standard Extension ***
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cbo_clean 0000000 00001 ..... 010 00000 0001111 @sfence_vm
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cbo_flush 0000000 00010 ..... 010 00000 0001111 @sfence_vm
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cbo_inval 0000000 00000 ..... 010 00000 0001111 @sfence_vm
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# *** RV32 Zicboz Standard Extension ***
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cbo_zero 0000000 00100 ..... 010 00000 0001111 @sfence_vm
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]
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@ -16,12 +16,39 @@
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#define REQUIRE_ZICBOM(ctx) do { \
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if (!ctx->cfg_ptr->ext_icbom) { \
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return false; \
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} \
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} while (0)
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#define REQUIRE_ZICBOZ(ctx) do { \
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if (!ctx->cfg_ptr->ext_icboz) { \
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return false; \
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} \
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} while (0)
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static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a)
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{
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REQUIRE_ZICBOM(ctx);
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gen_helper_cbo_clean_flush(cpu_env, cpu_gpr[a->rs1]);
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return true;
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}
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static bool trans_cbo_flush(DisasContext *ctx, arg_cbo_flush *a)
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{
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REQUIRE_ZICBOM(ctx);
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gen_helper_cbo_clean_flush(cpu_env, cpu_gpr[a->rs1]);
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return true;
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}
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static bool trans_cbo_inval(DisasContext *ctx, arg_cbo_inval *a)
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{
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REQUIRE_ZICBOM(ctx);
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gen_helper_cbo_inval(cpu_env, cpu_gpr[a->rs1]);
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return true;
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}
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static bool trans_cbo_zero(DisasContext *ctx, arg_cbo_zero *a)
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{
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REQUIRE_ZICBOZ(ctx);
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@ -191,6 +191,73 @@ void helper_cbo_zero(CPURISCVState *env, target_ulong address)
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}
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}
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/*
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* check_zicbom_access
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*
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* Check access permissions (LOAD, STORE or FETCH as specified in
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* section 2.5.2 of the CMO specification) for Zicbom, raising
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* either store page-fault (non-virtualized) or store guest-page
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* fault (virtualized).
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*/
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static void check_zicbom_access(CPURISCVState *env,
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target_ulong address,
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uintptr_t ra)
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{
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RISCVCPU *cpu = env_archcpu(env);
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int mmu_idx = cpu_mmu_index(env, false);
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uint16_t cbomlen = cpu->cfg.cbom_blocksize;
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void *phost;
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int ret;
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/* Mask off low-bits to align-down to the cache-block. */
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address &= ~(cbomlen - 1);
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/*
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* Section 2.5.2 of cmobase v1.0.1:
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*
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* "A cache-block management instruction is permitted to
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* access the specified cache block whenever a load instruction
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* or store instruction is permitted to access the corresponding
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* physical addresses. If neither a load instruction nor store
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* instruction is permitted to access the physical addresses,
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* but an instruction fetch is permitted to access the physical
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* addresses, whether a cache-block management instruction is
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* permitted to access the cache block is UNSPECIFIED."
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*/
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ret = probe_access_flags(env, address, cbomlen, MMU_DATA_LOAD,
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mmu_idx, true, &phost, ra);
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if (ret != TLB_INVALID_MASK) {
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/* Success: readable */
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return;
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}
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/*
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* Since not readable, must be writable. On failure, store
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* fault/store guest amo fault will be raised by
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* riscv_cpu_tlb_fill(). PMP exceptions will be caught
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* there as well.
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*/
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probe_write(env, address, cbomlen, mmu_idx, ra);
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}
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void helper_cbo_clean_flush(CPURISCVState *env, target_ulong address)
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{
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uintptr_t ra = GETPC();
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check_zicbo_envcfg(env, MENVCFG_CBCFE, ra);
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check_zicbom_access(env, address, ra);
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/* We don't emulate the cache-hierarchy, so we're done. */
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}
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void helper_cbo_inval(CPURISCVState *env, target_ulong address)
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{
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uintptr_t ra = GETPC();
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check_zicbo_envcfg(env, MENVCFG_CBIE, ra);
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check_zicbom_access(env, address, ra);
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/* We don't emulate the cache-hierarchy, so we're done. */
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}
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#ifndef CONFIG_USER_ONLY
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target_ulong helper_sret(CPURISCVState *env)
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