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sh7750: handle MMUCR TI bit

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When the MMUCR TI bit is set, all the UTLB and ITLB entries should be
flushed.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Aurelien Jarno 2010-02-02 19:39:11 +01:00
parent 434254aa5f
commit e0bcb9ca36
3 changed files with 25 additions and 2 deletions
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7
hw/sh7750.c
View File

@ -396,8 +396,11 @@ static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
portb_changed(s, temp);
return;
case SH7750_MMUCR_A7:
s->cpu->mmucr = mem_value;
return;
if (mem_value & MMUCR_TI) {
cpu_sh4_invalidate_tlb(s->cpu);
}
s->cpu->mmucr = mem_value & ~MMUCR_TI;
return;
case SH7750_PTEH_A7:
/* If asid changes, clear all registered tlb entries. */
if ((s->cpu->pteh & 0xff) != (mem_value & 0xff))

2
target-sh4/cpu.h
View File

@ -167,6 +167,7 @@ int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw,
void do_interrupt(CPUSH4State * env);
void sh4_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
void cpu_sh4_invalidate_tlb(CPUSH4State *s);
void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
uint32_t mem_value);
@ -222,6 +223,7 @@ enum {
/* MMU control register */
#define MMUCR 0x1F000010
#define MMUCR_AT (1<<0)
#define MMUCR_TI (1<<2)
#define MMUCR_SV (1<<8)
#define MMUCR_URC_BITS (6)
#define MMUCR_URC_OFFSET (10)

18
target-sh4/helper.c
View File

@ -574,6 +574,24 @@ void cpu_load_tlb(CPUSH4State * env)
entry->tc = (uint8_t)cpu_ptea_tc(env->ptea);
}
void cpu_sh4_invalidate_tlb(CPUSH4State *s)
{
int i;
/* UTLB */
for (i = 0; i < UTLB_SIZE; i++) {
tlb_t * entry = &s->utlb[i];
entry->v = 0;
}
/* ITLB */
for (i = 0; i < UTLB_SIZE; i++) {
tlb_t * entry = &s->utlb[i];
entry->v = 0;
}
tlb_flush(s, 1);
}
void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
uint32_t mem_value)
{