sh7750: handle MMUCR TI bit
When the MMUCR TI bit is set, all the UTLB and ITLB entries should be flushed. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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@ -396,7 +396,10 @@ static void sh7750_mem_writel(void *opaque, target_phys_addr_t addr,
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portb_changed(s, temp);
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return;
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case SH7750_MMUCR_A7:
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s->cpu->mmucr = mem_value;
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if (mem_value & MMUCR_TI) {
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cpu_sh4_invalidate_tlb(s->cpu);
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}
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s->cpu->mmucr = mem_value & ~MMUCR_TI;
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return;
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case SH7750_PTEH_A7:
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/* If asid changes, clear all registered tlb entries. */
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@ -167,6 +167,7 @@ int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw,
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void do_interrupt(CPUSH4State * env);
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void sh4_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
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void cpu_sh4_invalidate_tlb(CPUSH4State *s);
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void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
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uint32_t mem_value);
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@ -222,6 +223,7 @@ enum {
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/* MMU control register */
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#define MMUCR 0x1F000010
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#define MMUCR_AT (1<<0)
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#define MMUCR_TI (1<<2)
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#define MMUCR_SV (1<<8)
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#define MMUCR_URC_BITS (6)
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#define MMUCR_URC_OFFSET (10)
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@ -574,6 +574,24 @@ void cpu_load_tlb(CPUSH4State * env)
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entry->tc = (uint8_t)cpu_ptea_tc(env->ptea);
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}
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void cpu_sh4_invalidate_tlb(CPUSH4State *s)
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{
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int i;
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/* UTLB */
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for (i = 0; i < UTLB_SIZE; i++) {
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tlb_t * entry = &s->utlb[i];
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entry->v = 0;
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}
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/* ITLB */
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for (i = 0; i < UTLB_SIZE; i++) {
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tlb_t * entry = &s->utlb[i];
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entry->v = 0;
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}
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tlb_flush(s, 1);
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}
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void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
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uint32_t mem_value)
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{
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