hw/nvme: basic directives support
Add support for the Directive Send and Recv commands and the Identify directive. Reviewed-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Gollu Appalanaidu <anaidu.gollu@samsung.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
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@ -266,6 +266,8 @@ static const uint32_t nvme_cse_acs[256] = {
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[NVME_ADM_CMD_VIRT_MNGMT] = NVME_CMD_EFF_CSUPP,
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[NVME_ADM_CMD_DBBUF_CONFIG] = NVME_CMD_EFF_CSUPP,
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[NVME_ADM_CMD_FORMAT_NVM] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC,
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[NVME_ADM_CMD_DIRECTIVE_RECV] = NVME_CMD_EFF_CSUPP,
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[NVME_ADM_CMD_DIRECTIVE_SEND] = NVME_CMD_EFF_CSUPP,
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};
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static const uint32_t nvme_cse_iocs_none[256];
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@ -6150,6 +6152,37 @@ static uint16_t nvme_dbbuf_config(NvmeCtrl *n, const NvmeRequest *req)
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return NVME_SUCCESS;
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}
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static uint16_t nvme_directive_send(NvmeCtrl *n, NvmeRequest *req)
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{
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return NVME_INVALID_FIELD | NVME_DNR;
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}
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static uint16_t nvme_directive_receive(NvmeCtrl *n, NvmeRequest *req)
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{
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uint32_t dw10 = le32_to_cpu(req->cmd.cdw10);
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uint32_t dw11 = le32_to_cpu(req->cmd.cdw11);
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uint32_t nsid = le32_to_cpu(req->cmd.nsid);
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uint8_t doper, dtype;
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uint32_t numd, trans_len;
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NvmeDirectiveIdentify id = {
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.supported = 1 << NVME_DIRECTIVE_IDENTIFY,
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.enabled = 1 << NVME_DIRECTIVE_IDENTIFY,
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};
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numd = dw10 + 1;
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doper = dw11 & 0xff;
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dtype = (dw11 >> 8) & 0xff;
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trans_len = MIN(sizeof(NvmeDirectiveIdentify), numd << 2);
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if (nsid == NVME_NSID_BROADCAST || dtype != NVME_DIRECTIVE_IDENTIFY ||
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doper != NVME_DIRECTIVE_RETURN_PARAMS) {
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return NVME_INVALID_FIELD | NVME_DNR;
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}
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return nvme_c2h(n, (uint8_t *)&id, trans_len, req);
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}
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static uint16_t nvme_admin_cmd(NvmeCtrl *n, NvmeRequest *req)
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{
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trace_pci_nvme_admin_cmd(nvme_cid(req), nvme_sqid(req), req->cmd.opcode,
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@ -6198,6 +6231,10 @@ static uint16_t nvme_admin_cmd(NvmeCtrl *n, NvmeRequest *req)
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return nvme_dbbuf_config(n, req);
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case NVME_ADM_CMD_FORMAT_NVM:
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return nvme_format(n, req);
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case NVME_ADM_CMD_DIRECTIVE_SEND:
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return nvme_directive_send(n, req);
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case NVME_ADM_CMD_DIRECTIVE_RECV:
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return nvme_directive_receive(n, req);
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default:
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assert(false);
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}
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@ -7454,7 +7491,8 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev)
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id->mdts = n->params.mdts;
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id->ver = cpu_to_le32(NVME_SPEC_VER);
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id->oacs =
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cpu_to_le16(NVME_OACS_NS_MGMT | NVME_OACS_FORMAT | NVME_OACS_DBBUF);
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cpu_to_le16(NVME_OACS_NS_MGMT | NVME_OACS_FORMAT | NVME_OACS_DBBUF |
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NVME_OACS_DIRECTIVES);
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id->cntrltype = 0x1;
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/*
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@ -345,7 +345,9 @@ static inline const char *nvme_adm_opc_str(uint8_t opc)
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case NVME_ADM_CMD_GET_FEATURES: return "NVME_ADM_CMD_GET_FEATURES";
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case NVME_ADM_CMD_ASYNC_EV_REQ: return "NVME_ADM_CMD_ASYNC_EV_REQ";
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case NVME_ADM_CMD_NS_ATTACHMENT: return "NVME_ADM_CMD_NS_ATTACHMENT";
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case NVME_ADM_CMD_DIRECTIVE_SEND: return "NVME_ADM_CMD_DIRECTIVE_SEND";
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case NVME_ADM_CMD_VIRT_MNGMT: return "NVME_ADM_CMD_VIRT_MNGMT";
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case NVME_ADM_CMD_DIRECTIVE_RECV: return "NVME_ADM_CMD_DIRECTIVE_RECV";
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case NVME_ADM_CMD_DBBUF_CONFIG: return "NVME_ADM_CMD_DBBUF_CONFIG";
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case NVME_ADM_CMD_FORMAT_NVM: return "NVME_ADM_CMD_FORMAT_NVM";
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default: return "NVME_ADM_CMD_UNKNOWN";
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@ -613,7 +613,9 @@ enum NvmeAdminCommands {
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NVME_ADM_CMD_ACTIVATE_FW = 0x10,
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NVME_ADM_CMD_DOWNLOAD_FW = 0x11,
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NVME_ADM_CMD_NS_ATTACHMENT = 0x15,
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NVME_ADM_CMD_DIRECTIVE_SEND = 0x19,
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NVME_ADM_CMD_VIRT_MNGMT = 0x1c,
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NVME_ADM_CMD_DIRECTIVE_RECV = 0x1a,
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NVME_ADM_CMD_DBBUF_CONFIG = 0x7c,
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NVME_ADM_CMD_FORMAT_NVM = 0x80,
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NVME_ADM_CMD_SECURITY_SEND = 0x81,
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@ -1161,11 +1163,12 @@ enum NvmeIdCtrlCtratt {
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};
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enum NvmeIdCtrlOacs {
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NVME_OACS_SECURITY = 1 << 0,
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NVME_OACS_FORMAT = 1 << 1,
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NVME_OACS_FW = 1 << 2,
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NVME_OACS_NS_MGMT = 1 << 3,
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NVME_OACS_DBBUF = 1 << 8,
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NVME_OACS_SECURITY = 1 << 0,
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NVME_OACS_FORMAT = 1 << 1,
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NVME_OACS_FW = 1 << 2,
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NVME_OACS_NS_MGMT = 1 << 3,
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NVME_OACS_DIRECTIVES = 1 << 5,
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NVME_OACS_DBBUF = 1 << 8,
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};
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enum NvmeIdCtrlOncs {
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@ -1644,6 +1647,27 @@ typedef enum NvmeVirtualResourceType {
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NVME_VIRT_RES_INTERRUPT = 0x01,
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} NvmeVirtualResourceType;
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typedef struct NvmeDirectiveIdentify {
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uint8_t supported;
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uint8_t unused1[31];
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uint8_t enabled;
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uint8_t unused33[31];
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uint8_t rsvd64[4032];
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} NvmeDirectiveIdentify;
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enum NvmeDirective {
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NVME_DIRECTIVE_SUPPORTED = 0x0,
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NVME_DIRECTIVE_ENABLED = 0x1,
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};
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enum NvmeDirectiveTypes {
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NVME_DIRECTIVE_IDENTIFY = 0x0,
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};
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enum NvmeDirectiveOperations {
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NVME_DIRECTIVE_RETURN_PARAMS = 0x1,
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};
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static inline void _nvme_check_size(void)
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{
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QEMU_BUILD_BUG_ON(sizeof(NvmeBar) != 4096);
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@ -1683,5 +1707,6 @@ static inline void _nvme_check_size(void)
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QEMU_BUILD_BUG_ON(sizeof(NvmeSecCtrlEntry) != 32);
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QEMU_BUILD_BUG_ON(sizeof(NvmeSecCtrlList) != 4096);
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QEMU_BUILD_BUG_ON(sizeof(NvmeEndGrpLog) != 512);
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QEMU_BUILD_BUG_ON(sizeof(NvmeDirectiveIdentify) != 4096);
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}
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#endif
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