diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 874ecee5ee..cf7043a576 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -142,7 +142,6 @@ struct CPUMIPSState {
     target_ulong PC[MIPS_TC_MAX];
 #if TARGET_LONG_BITS > HOST_LONG_BITS
     target_ulong t0;
-    target_ulong t1;
 #endif
     /* temporary hack for FP globals */
 #ifndef USE_HOST_FLOAT_REGS
diff --git a/target-mips/exec.h b/target-mips/exec.h
index 2653d34c7d..6b351da114 100644
--- a/target-mips/exec.h
+++ b/target-mips/exec.h
@@ -12,10 +12,8 @@ register struct CPUMIPSState *env asm(AREG0);
 
 #if TARGET_LONG_BITS > HOST_LONG_BITS
 #define T0 (env->t0)
-#define T1 (env->t1)
 #else
 register target_ulong T0 asm(AREG1);
-register target_ulong T1 asm(AREG2);
 #endif
 
 #if defined (USE_HOST_FLOAT_REGS)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index de2ee21836..106d355923 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -423,7 +423,7 @@ enum {
 };
 
 /* global register indices */
-static TCGv cpu_env, current_tc_gprs, current_tc_hi, current_fpu, cpu_T[2];
+static TCGv cpu_env, current_tc_gprs, current_tc_hi, current_fpu, cpu_T[1];
 
 /* FPU TNs, global for now. */
 static TCGv fpu32_T[3], fpu64_T[3], fpu32h_T[3];
@@ -8072,11 +8072,8 @@ static void mips_tcg_init(void)
 #if TARGET_LONG_BITS > HOST_LONG_BITS
     cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
                                   TCG_AREG0, offsetof(CPUState, t0), "T0");
-    cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
-                                  TCG_AREG0, offsetof(CPUState, t1), "T1");
 #else
     cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
-    cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
 #endif
 
     /* register helpers */