pxa2xx_pic: update to use qdev
Use qdev/sysbus framework to handle pxa2xx-pic. Instead of exposing IRQs via array, reference them via qdev_get_gpio_in(). Patch has been modified by the committer. Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
This commit is contained in:
Dmitry Eremin-Solenikov
Andrzej Zaborowski
parent
3e1dbc3bd4
commit
e1f8c729fa
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@ -140,7 +140,7 @@ static void mainstone_common_init(ram_addr_t ram_size,
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}
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mst_irq = sysbus_create_simple("mainstone-fpga", MST_FPGA_PHYS,
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cpu->pic[PXA2XX_PIC_GPIO_0]);
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qdev_get_gpio_in(cpu->pic, PXA2XX_PIC_GPIO_0));
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/* setup keypad */
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printf("map addr %p\n", &map);
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11
hw/pxa.h
11
hw/pxa.h
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@ -63,15 +63,15 @@
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# define PXA2XX_INTERNAL_SIZE 0x40000
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/* pxa2xx_pic.c */
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qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env);
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DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env);
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/* pxa2xx_timer.c */
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void pxa25x_timer_init(target_phys_addr_t base, qemu_irq *irqs);
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void pxa27x_timer_init(target_phys_addr_t base, qemu_irq *irqs, qemu_irq irq4);
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void pxa25x_timer_init(target_phys_addr_t base, DeviceState *pic);
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void pxa27x_timer_init(target_phys_addr_t base, DeviceState *pic);
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/* pxa2xx_gpio.c */
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DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
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CPUState *env, qemu_irq *pic, int lines);
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CPUState *env, DeviceState *pic, int lines);
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void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler);
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/* pxa2xx_dma.c */
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@ -125,7 +125,7 @@ typedef struct PXA2xxFIrState PXA2xxFIrState;
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typedef struct {
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CPUState *env;
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qemu_irq *pic;
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DeviceState *pic;
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qemu_irq reset;
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PXA2xxDMAState *dma;
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DeviceState *gpio;
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@ -180,6 +180,7 @@ typedef struct {
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QEMUTimer *rtc_swal1;
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QEMUTimer *rtc_swal2;
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QEMUTimer *rtc_pi;
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qemu_irq rtc_irq;
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} PXA2xxState;
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struct PXA2xxI2SState {
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76
hw/pxa2xx.c
76
hw/pxa2xx.c
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@ -888,7 +888,7 @@ static int pxa2xx_ssp_init(SysBusDevice *dev)
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static inline void pxa2xx_rtc_int_update(PXA2xxState *s)
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{
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qemu_set_irq(s->pic[PXA2XX_PIC_RTCALARM], !!(s->rtsr & 0x2553));
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qemu_set_irq(s->rtc_irq, !!(s->rtsr & 0x2553));
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}
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static void pxa2xx_rtc_hzupdate(PXA2xxState *s)
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@ -1197,6 +1197,8 @@ static void pxa2xx_rtc_init(PXA2xxState *s)
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s->rtc_swal1 = qemu_new_timer(rt_clock, pxa2xx_rtc_swal1_tick, s);
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s->rtc_swal2 = qemu_new_timer(rt_clock, pxa2xx_rtc_swal2_tick, s);
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s->rtc_pi = qemu_new_timer(rt_clock, pxa2xx_rtc_pi_tick, s);
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s->rtc_irq = qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM);
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}
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static void pxa2xx_rtc_save(QEMUFile *f, void *opaque)
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@ -2095,10 +2097,10 @@ PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision)
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s->pic = pxa2xx_pic_init(0x40d00000, s->env);
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s->dma = pxa27x_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]);
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s->dma = pxa27x_dma_init(0x40000000,
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qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
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pxa27x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0],
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s->pic[PXA27X_PIC_OST_4_11]);
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pxa27x_timer_init(0x40a00000, s->pic);
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s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 121);
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@ -2108,26 +2110,28 @@ PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision)
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exit(1);
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}
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s->mmc = pxa2xx_mmci_init(0x41100000, dinfo->bdrv,
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s->pic[PXA2XX_PIC_MMC], s->dma);
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qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), s->dma);
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for (i = 0; pxa270_serial[i].io_base; i ++)
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if (serial_hds[i])
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#ifdef TARGET_WORDS_BIGENDIAN
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serial_mm_init(pxa270_serial[i].io_base, 2,
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s->pic[pxa270_serial[i].irqn], 14857000/16,
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serial_hds[i], 1, 1);
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qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn),
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14857000 / 16, serial_hds[i], 1, 1);
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#else
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serial_mm_init(pxa270_serial[i].io_base, 2,
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s->pic[pxa270_serial[i].irqn], 14857000/16,
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serial_hds[i], 1, 0);
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qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn),
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14857000 / 16, serial_hds[i], 1, 0);
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#endif
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else
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break;
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if (serial_hds[i])
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s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
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s->fir = pxa2xx_fir_init(0x40800000,
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qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
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s->dma, serial_hds[i]);
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s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD]);
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s->lcd = pxa2xx_lcdc_init(0x44000000,
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qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
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s->cm_base = 0x41300000;
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s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
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@ -2159,13 +2163,13 @@ PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision)
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for (i = 0; pxa27x_ssp[i].io_base; i ++) {
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DeviceState *dev;
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dev = sysbus_create_simple("pxa2xx-ssp", pxa27x_ssp[i].io_base,
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s->pic[pxa27x_ssp[i].irqn]);
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qdev_get_gpio_in(s->pic, pxa27x_ssp[i].irqn));
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s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
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}
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if (usb_enabled) {
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sysbus_create_simple("sysbus-ohci", 0x4c000000,
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s->pic[PXA2XX_PIC_USBH1]);
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qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
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}
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s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
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@ -2179,12 +2183,16 @@ PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision)
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register_savevm(NULL, "pxa2xx_rtc", 0, 0, pxa2xx_rtc_save,
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pxa2xx_rtc_load, s);
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s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 0xffff);
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s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0xff);
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s->i2c[0] = pxa2xx_i2c_init(0x40301600,
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qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
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s->i2c[1] = pxa2xx_i2c_init(0x40f00100,
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qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
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s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
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s->i2s = pxa2xx_i2s_init(0x40400000,
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qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), s->dma);
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s->kp = pxa27x_keypad_init(0x41500000, s->pic[PXA2XX_PIC_KEYPAD]);
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s->kp = pxa27x_keypad_init(0x41500000,
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qdev_get_gpio_in(s->pic, PXA2XX_PIC_KEYPAD));
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/* GPIO1 resets the processor */
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/* The handler can be overridden by board-specific code */
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@ -2218,9 +2226,10 @@ PXA2xxState *pxa255_init(unsigned int sdram_size)
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s->pic = pxa2xx_pic_init(0x40d00000, s->env);
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s->dma = pxa255_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]);
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s->dma = pxa255_dma_init(0x40000000,
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qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
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pxa25x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0]);
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pxa25x_timer_init(0x40a00000, s->pic);
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s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 85);
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@ -2230,27 +2239,29 @@ PXA2xxState *pxa255_init(unsigned int sdram_size)
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exit(1);
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}
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s->mmc = pxa2xx_mmci_init(0x41100000, dinfo->bdrv,
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s->pic[PXA2XX_PIC_MMC], s->dma);
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qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), s->dma);
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for (i = 0; pxa255_serial[i].io_base; i ++)
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if (serial_hds[i]) {
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#ifdef TARGET_WORDS_BIGENDIAN
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serial_mm_init(pxa255_serial[i].io_base, 2,
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s->pic[pxa255_serial[i].irqn], 14745600/16,
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serial_hds[i], 1, 1);
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qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn),
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14745600 / 16, serial_hds[i], 1, 1);
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#else
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serial_mm_init(pxa255_serial[i].io_base, 2,
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s->pic[pxa255_serial[i].irqn], 14745600/16,
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serial_hds[i], 1, 0);
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qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn),
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14745600 / 16, serial_hds[i], 1, 0);
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#endif
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} else {
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break;
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}
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if (serial_hds[i])
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s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
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s->fir = pxa2xx_fir_init(0x40800000,
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qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
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s->dma, serial_hds[i]);
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s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD]);
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s->lcd = pxa2xx_lcdc_init(0x44000000,
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qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
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s->cm_base = 0x41300000;
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s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
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@ -2282,13 +2293,13 @@ PXA2xxState *pxa255_init(unsigned int sdram_size)
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for (i = 0; pxa255_ssp[i].io_base; i ++) {
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DeviceState *dev;
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dev = sysbus_create_simple("pxa2xx-ssp", pxa255_ssp[i].io_base,
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s->pic[pxa255_ssp[i].irqn]);
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qdev_get_gpio_in(s->pic, pxa255_ssp[i].irqn));
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s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
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}
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if (usb_enabled) {
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sysbus_create_simple("sysbus-ohci", 0x4c000000,
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s->pic[PXA2XX_PIC_USBH1]);
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qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
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}
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s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
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@ -2302,10 +2313,13 @@ PXA2xxState *pxa255_init(unsigned int sdram_size)
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register_savevm(NULL, "pxa2xx_rtc", 0, 0, pxa2xx_rtc_save,
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pxa2xx_rtc_load, s);
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s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 0xffff);
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s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0xff);
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s->i2c[0] = pxa2xx_i2c_init(0x40301600,
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qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
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s->i2c[1] = pxa2xx_i2c_init(0x40f00100,
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qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
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s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
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s->i2s = pxa2xx_i2s_init(0x40400000,
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qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), s->dma);
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/* GPIO1 resets the processor */
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/* The handler can be overridden by board-specific code */
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@ -253,7 +253,7 @@ static CPUWriteMemoryFunc * const pxa2xx_gpio_writefn[] = {
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};
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DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
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CPUState *env, qemu_irq *pic, int lines)
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CPUState *env, DeviceState *pic, int lines)
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{
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DeviceState *dev;
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@ -263,9 +263,12 @@ DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
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qdev_init_nofail(dev);
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sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
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sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[PXA2XX_PIC_GPIO_0]);
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sysbus_connect_irq(sysbus_from_qdev(dev), 1, pic[PXA2XX_PIC_GPIO_1]);
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sysbus_connect_irq(sysbus_from_qdev(dev), 2, pic[PXA2XX_PIC_GPIO_X]);
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sysbus_connect_irq(sysbus_from_qdev(dev), 0,
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qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_0));
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sysbus_connect_irq(sysbus_from_qdev(dev), 1,
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qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_1));
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sysbus_connect_irq(sysbus_from_qdev(dev), 2,
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qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_X));
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return dev;
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}
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@ -10,6 +10,7 @@
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#include "hw.h"
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#include "pxa.h"
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#include "sysbus.h"
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#define ICIP 0x00 /* Interrupt Controller IRQ Pending register */
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#define ICMR 0x04 /* Interrupt Controller Mask register */
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@ -31,6 +32,7 @@
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#define PXA2XX_PIC_SRCS 40
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typedef struct {
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SysBusDevice busdev;
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CPUState *cpu_env;
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uint32_t int_enabled[2];
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uint32_t int_pending[2];
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@ -241,51 +243,17 @@ static CPUWriteMemoryFunc * const pxa2xx_pic_writefn[] = {
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pxa2xx_pic_mem_write,
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};
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static void pxa2xx_pic_save(QEMUFile *f, void *opaque)
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static int pxa2xx_pic_post_load(void *opaque, int version_id)
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{
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PXA2xxPICState *s = (PXA2xxPICState *) opaque;
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int i;
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for (i = 0; i < 2; i ++)
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qemu_put_be32s(f, &s->int_enabled[i]);
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for (i = 0; i < 2; i ++)
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qemu_put_be32s(f, &s->int_pending[i]);
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for (i = 0; i < 2; i ++)
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qemu_put_be32s(f, &s->is_fiq[i]);
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qemu_put_be32s(f, &s->int_idle);
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for (i = 0; i < PXA2XX_PIC_SRCS; i ++)
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qemu_put_be32s(f, &s->priority[i]);
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}
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static int pxa2xx_pic_load(QEMUFile *f, void *opaque, int version_id)
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{
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PXA2xxPICState *s = (PXA2xxPICState *) opaque;
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int i;
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for (i = 0; i < 2; i ++)
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qemu_get_be32s(f, &s->int_enabled[i]);
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for (i = 0; i < 2; i ++)
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qemu_get_be32s(f, &s->int_pending[i]);
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for (i = 0; i < 2; i ++)
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qemu_get_be32s(f, &s->is_fiq[i]);
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qemu_get_be32s(f, &s->int_idle);
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for (i = 0; i < PXA2XX_PIC_SRCS; i ++)
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qemu_get_be32s(f, &s->priority[i]);
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pxa2xx_pic_update(opaque);
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return 0;
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}
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qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env)
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DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env)
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{
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PXA2xxPICState *s;
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DeviceState *dev = qdev_create(NULL, "pxa2xx_pic");
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int iomemtype;
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qemu_irq *qi;
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s = (PXA2xxPICState *)
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qemu_mallocz(sizeof(PXA2xxPICState));
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if (!s)
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return NULL;
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PXA2xxPICState *s = FROM_SYSBUS(PXA2xxPICState, sysbus_from_qdev(dev));
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||||
|
||||
s->cpu_env = env;
|
||||
|
||||
|
|
@ -296,18 +264,52 @@ qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env)
|
|||
s->is_fiq[0] = 0;
|
||||
s->is_fiq[1] = 0;
|
||||
|
||||
qi = qemu_allocate_irqs(pxa2xx_pic_set_irq, s, PXA2XX_PIC_SRCS);
|
||||
qdev_init_nofail(dev);
|
||||
|
||||
qdev_init_gpio_in(dev, pxa2xx_pic_set_irq, PXA2XX_PIC_SRCS);
|
||||
|
||||
/* Enable IC memory-mapped registers access. */
|
||||
iomemtype = cpu_register_io_memory(pxa2xx_pic_readfn,
|
||||
pxa2xx_pic_writefn, s, DEVICE_NATIVE_ENDIAN);
|
||||
cpu_register_physical_memory(base, 0x00100000, iomemtype);
|
||||
sysbus_init_mmio(sysbus_from_qdev(dev), 0x00100000, iomemtype);
|
||||
|
||||
/* Enable IC coprocessor access. */
|
||||
cpu_arm_set_cp_io(env, 6, pxa2xx_pic_cp_read, pxa2xx_pic_cp_write, s);
|
||||
|
||||
register_savevm(NULL, "pxa2xx_pic", 0, 0, pxa2xx_pic_save,
|
||||
pxa2xx_pic_load, s);
|
||||
|
||||
return qi;
|
||||
return dev;
|
||||
}
|
||||
|
||||
static VMStateDescription vmstate_pxa2xx_pic_regs = {
|
||||
.name = "pxa2xx_pic",
|
||||
.version_id = 0,
|
||||
.minimum_version_id = 0,
|
||||
.minimum_version_id_old = 0,
|
||||
.post_load = pxa2xx_pic_post_load,
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_UINT32_ARRAY(int_enabled, PXA2xxPICState, 2),
|
||||
VMSTATE_UINT32_ARRAY(int_pending, PXA2xxPICState, 2),
|
||||
VMSTATE_UINT32_ARRAY(is_fiq, PXA2xxPICState, 2),
|
||||
VMSTATE_UINT32(int_idle, PXA2xxPICState),
|
||||
VMSTATE_UINT32_ARRAY(priority, PXA2xxPICState, PXA2XX_PIC_SRCS),
|
||||
VMSTATE_END_OF_LIST(),
|
||||
},
|
||||
};
|
||||
|
||||
static int pxa2xx_pic_initfn(SysBusDevice *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static SysBusDeviceInfo pxa2xx_pic_info = {
|
||||
.init = pxa2xx_pic_initfn,
|
||||
.qdev.name = "pxa2xx_pic",
|
||||
.qdev.desc = "PXA2xx PIC",
|
||||
.qdev.size = sizeof(PXA2xxPICState),
|
||||
.qdev.vmsd = &vmstate_pxa2xx_pic_regs,
|
||||
};
|
||||
|
||||
static void pxa2xx_pic_register(void)
|
||||
{
|
||||
sysbus_register_withprop(&pxa2xx_pic_info);
|
||||
}
|
||||
device_init(pxa2xx_pic_register);
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@
|
|||
#include "hw.h"
|
||||
#include "qemu-timer.h"
|
||||
#include "sysemu.h"
|
||||
#include "qdev.h"
|
||||
#include "pxa.h"
|
||||
|
||||
#define OSMR0 0x00
|
||||
|
|
@ -428,7 +429,7 @@ static int pxa2xx_timer_load(QEMUFile *f, void *opaque, int version_id)
|
|||
}
|
||||
|
||||
static pxa2xx_timer_info *pxa2xx_timer_init(target_phys_addr_t base,
|
||||
qemu_irq *irqs)
|
||||
DeviceState *pic)
|
||||
{
|
||||
int i;
|
||||
int iomemtype;
|
||||
|
|
@ -443,7 +444,7 @@ static pxa2xx_timer_info *pxa2xx_timer_init(target_phys_addr_t base,
|
|||
|
||||
for (i = 0; i < 4; i ++) {
|
||||
s->timer[i].value = 0;
|
||||
s->timer[i].irq = irqs[i];
|
||||
s->timer[i].irq = qdev_get_gpio_in(pic, PXA2XX_PIC_OST_0 + i);
|
||||
s->timer[i].info = s;
|
||||
s->timer[i].num = i;
|
||||
s->timer[i].level = 0;
|
||||
|
|
@ -461,24 +462,23 @@ static pxa2xx_timer_info *pxa2xx_timer_init(target_phys_addr_t base,
|
|||
return s;
|
||||
}
|
||||
|
||||
void pxa25x_timer_init(target_phys_addr_t base, qemu_irq *irqs)
|
||||
void pxa25x_timer_init(target_phys_addr_t base, DeviceState *pic)
|
||||
{
|
||||
pxa2xx_timer_info *s = pxa2xx_timer_init(base, irqs);
|
||||
pxa2xx_timer_info *s = pxa2xx_timer_init(base, pic);
|
||||
s->freq = PXA25X_FREQ;
|
||||
s->tm4 = NULL;
|
||||
}
|
||||
|
||||
void pxa27x_timer_init(target_phys_addr_t base,
|
||||
qemu_irq *irqs, qemu_irq irq4)
|
||||
void pxa27x_timer_init(target_phys_addr_t base, DeviceState *pic)
|
||||
{
|
||||
pxa2xx_timer_info *s = pxa2xx_timer_init(base, irqs);
|
||||
pxa2xx_timer_info *s = pxa2xx_timer_init(base, pic);
|
||||
int i;
|
||||
s->freq = PXA27X_FREQ;
|
||||
s->tm4 = (PXA2xxTimer4 *) qemu_mallocz(8 *
|
||||
sizeof(PXA2xxTimer4));
|
||||
for (i = 0; i < 8; i ++) {
|
||||
s->tm4[i].tm.value = 0;
|
||||
s->tm4[i].tm.irq = irq4;
|
||||
s->tm4[i].tm.irq = qdev_get_gpio_in(pic, PXA27X_PIC_OST_4_11);
|
||||
s->tm4[i].tm.info = s;
|
||||
s->tm4[i].tm.num = i + 4;
|
||||
s->tm4[i].tm.level = 0;
|
||||
|
|
|
|||
Loading…
Reference in New Issue