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target/riscv: mcountinhibit, mcounteren, scounteren, hcounteren is 32-bit

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mcountinhibit, mcounteren, scounteren and hcounteren must always be 32-bit
by privileged spec

Signed-off-by: Vadim Shakirov <vadim.shakirov@syntacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20240202113919.18236-1-vadim.shakirov@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Vadim Shakirov 2024-02-02 14:39:19 +03:00 committed by Alistair Francis
parent 249e0905d0
commit e231ec8f67
2 changed files with 12 additions and 12 deletions
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8
target/riscv/cpu.h
View File

@ -271,7 +271,7 @@ struct CPUArchState {
target_ulong hstatus; target_ulong hstatus;
target_ulong hedeleg; target_ulong hedeleg;
uint64_t hideleg; uint64_t hideleg;
target_ulong hcounteren; uint32_t hcounteren;
target_ulong htval; target_ulong htval;
target_ulong htinst; target_ulong htinst;
target_ulong hgatp; target_ulong hgatp;
@ -334,10 +334,10 @@ struct CPUArchState {
*/ */
bool two_stage_indirect_lookup; bool two_stage_indirect_lookup;
target_ulong scounteren; uint32_t scounteren;
target_ulong mcounteren; uint32_t mcounteren;
target_ulong mcountinhibit; uint32_t mcountinhibit;
/* PMU counter state */ /* PMU counter state */
PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS];

16
target/riscv/machine.c
View File

@ -79,14 +79,14 @@ static bool hyper_needed(void *opaque)
static const VMStateDescription vmstate_hyper = { static const VMStateDescription vmstate_hyper = {
.name = "cpu/hyper", .name = "cpu/hyper",
.version_id = 3, .version_id = 4,
.minimum_version_id = 3, .minimum_version_id = 4,
.needed = hyper_needed, .needed = hyper_needed,
.fields = (const VMStateField[]) { .fields = (const VMStateField[]) {
VMSTATE_UINTTL(env.hstatus, RISCVCPU), VMSTATE_UINTTL(env.hstatus, RISCVCPU),
VMSTATE_UINTTL(env.hedeleg, RISCVCPU), VMSTATE_UINTTL(env.hedeleg, RISCVCPU),
VMSTATE_UINT64(env.hideleg, RISCVCPU), VMSTATE_UINT64(env.hideleg, RISCVCPU),
VMSTATE_UINTTL(env.hcounteren, RISCVCPU), VMSTATE_UINT32(env.hcounteren, RISCVCPU),
VMSTATE_UINTTL(env.htval, RISCVCPU), VMSTATE_UINTTL(env.htval, RISCVCPU),
VMSTATE_UINTTL(env.htinst, RISCVCPU), VMSTATE_UINTTL(env.htinst, RISCVCPU),
VMSTATE_UINTTL(env.hgatp, RISCVCPU), VMSTATE_UINTTL(env.hgatp, RISCVCPU),
@ -353,8 +353,8 @@ static const VMStateDescription vmstate_jvt = {
const VMStateDescription vmstate_riscv_cpu = { const VMStateDescription vmstate_riscv_cpu = {
.name = "cpu", .name = "cpu",
.version_id = 9, .version_id = 10,
.minimum_version_id = 9, .minimum_version_id = 10,
.post_load = riscv_cpu_post_load, .post_load = riscv_cpu_post_load,
.fields = (const VMStateField[]) { .fields = (const VMStateField[]) {
VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
@ -397,9 +397,9 @@ const VMStateDescription vmstate_riscv_cpu = {
VMSTATE_UINTTL(env.mtval, RISCVCPU), VMSTATE_UINTTL(env.mtval, RISCVCPU),
VMSTATE_UINTTL(env.miselect, RISCVCPU), VMSTATE_UINTTL(env.miselect, RISCVCPU),
VMSTATE_UINTTL(env.siselect, RISCVCPU), VMSTATE_UINTTL(env.siselect, RISCVCPU),
VMSTATE_UINTTL(env.scounteren, RISCVCPU), VMSTATE_UINT32(env.scounteren, RISCVCPU),
VMSTATE_UINTTL(env.mcounteren, RISCVCPU), VMSTATE_UINT32(env.mcounteren, RISCVCPU),
VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU), VMSTATE_UINT32(env.mcountinhibit, RISCVCPU),
VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, RV_MAX_MHPMCOUNTERS, 0, VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, RV_MAX_MHPMCOUNTERS, 0,
vmstate_pmu_ctr_state, PMUCTRState), vmstate_pmu_ctr_state, PMUCTRState),
VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENTS), VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENTS),