hw/arm/npcm7xx: Add EHCI and OHCI controllers
The NPCM730 and NPCM750 chips have a single USB host port shared between
a USB 2.0 EHCI host controller and a USB 1.1 OHCI host controller. This
adds support for both of them.
Testing notes:
* With -device usb-kbd, qemu will automatically insert a full-speed
hub, and the keyboard becomes controlled by the OHCI controller.
* With -device usb-kbd,bus=usb-bus.0,port=1, the keyboard is directly
attached to the port without any hubs, and the device becomes
controlled by the EHCI controller since it's high speed capable.
* With -device usb-kbd,bus=usb-bus.0,port=1,usb_version=1, the
keyboard is directly attached to the port, but it only advertises
itself as full-speed capable, so it becomes controlled by the OHCI
controller.
In all cases, the keyboard device enumerates correctly.
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Havard Skinnemoen
Peter Maydell
parent
326ccfe240
commit
e23e7b1259
@ -39,6 +39,7 @@ Supported devices
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* OTP controllers (no protection features)
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* Flash Interface Unit (FIU; no protection features)
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* Random Number Generator (RNG)
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* USB host (USBH)
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Missing devices
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---------------
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@ -54,7 +55,6 @@ Missing devices
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* eSPI slave interface
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* Ethernet controllers (GMAC and EMC)
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* USB host (USBH)
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* USB device (USBD)
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* SMBus controller (SMBF)
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* Peripheral SPI controller (PSPI)
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@ -46,6 +46,10 @@
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#define NPCM7XX_MC_BA (0xf0824000)
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#define NPCM7XX_RNG_BA (0xf000b000)
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/* USB Host modules */
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#define NPCM7XX_EHCI_BA (0xf0806000)
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#define NPCM7XX_OHCI_BA (0xf0807000)
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/* Internal AHB SRAM */
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#define NPCM7XX_RAM3_BA (0xc0008000)
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#define NPCM7XX_RAM3_SZ (4 * KiB)
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@ -90,6 +94,8 @@ enum NPCM7xxInterrupt {
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NPCM7XX_WDG0_IRQ = 47, /* Timer Module 0 Watchdog */
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NPCM7XX_WDG1_IRQ, /* Timer Module 1 Watchdog */
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NPCM7XX_WDG2_IRQ, /* Timer Module 2 Watchdog */
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NPCM7XX_EHCI_IRQ = 61,
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NPCM7XX_OHCI_IRQ = 62,
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};
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/* Total number of GIC interrupts, including internal Cortex-A9 interrupts. */
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@ -263,6 +269,9 @@ static void npcm7xx_init(Object *obj)
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object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
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}
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object_initialize_child(obj, "ehci", &s->ehci, TYPE_NPCM7XX_EHCI);
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object_initialize_child(obj, "ohci", &s->ohci, TYPE_SYSBUS_OHCI);
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QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu));
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for (i = 0; i < ARRAY_SIZE(s->fiu); i++) {
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object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i],
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@ -380,6 +389,22 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
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sysbus_realize(SYS_BUS_DEVICE(&s->rng), &error_abort);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->rng), 0, NPCM7XX_RNG_BA);
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/* USB Host */
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object_property_set_bool(OBJECT(&s->ehci), "companion-enable", true,
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&error_abort);
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sysbus_realize(SYS_BUS_DEVICE(&s->ehci), &error_abort);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci), 0, NPCM7XX_EHCI_BA);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci), 0,
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npcm7xx_irq(s, NPCM7XX_EHCI_IRQ));
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object_property_set_str(OBJECT(&s->ohci), "masterbus", "usb-bus.0",
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&error_abort);
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object_property_set_uint(OBJECT(&s->ohci), "num-ports", 1, &error_abort);
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sysbus_realize(SYS_BUS_DEVICE(&s->ohci), &error_abort);
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci), 0, NPCM7XX_OHCI_BA);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci), 0,
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npcm7xx_irq(s, NPCM7XX_OHCI_IRQ));
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/*
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* Flash Interface Unit (FIU). Can fail if incorrect number of chip selects
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* specified, but this is a programming error.
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@ -464,8 +489,6 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
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create_unimplemented_device("npcm7xx.mcphy", 0xf05f0000, 64 * KiB);
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create_unimplemented_device("npcm7xx.gmac1", 0xf0802000, 8 * KiB);
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create_unimplemented_device("npcm7xx.gmac2", 0xf0804000, 8 * KiB);
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create_unimplemented_device("npcm7xx.ehci", 0xf0806000, 4 * KiB);
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create_unimplemented_device("npcm7xx.ohci", 0xf0807000, 4 * KiB);
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create_unimplemented_device("npcm7xx.vcd", 0xf0810000, 64 * KiB);
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create_unimplemented_device("npcm7xx.ece", 0xf0820000, 8 * KiB);
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create_unimplemented_device("npcm7xx.vdma", 0xf0822000, 8 * KiB);
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@ -147,6 +147,24 @@ static const TypeInfo ehci_aw_h3_type_info = {
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.class_init = ehci_aw_h3_class_init,
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};
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static void ehci_npcm7xx_class_init(ObjectClass *oc, void *data)
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{
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SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
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DeviceClass *dc = DEVICE_CLASS(oc);
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sec->capsbase = 0x0;
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sec->opregbase = 0x10;
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sec->portscbase = 0x44;
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sec->portnr = 1;
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set_bit(DEVICE_CATEGORY_USB, dc->categories);
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}
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static const TypeInfo ehci_npcm7xx_type_info = {
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.name = TYPE_NPCM7XX_EHCI,
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.parent = TYPE_SYS_BUS_EHCI,
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.class_init = ehci_npcm7xx_class_init,
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};
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static void ehci_tegra2_class_init(ObjectClass *oc, void *data)
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{
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SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
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@ -269,6 +287,7 @@ static void ehci_sysbus_register_types(void)
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type_register_static(&ehci_platform_type_info);
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type_register_static(&ehci_exynos4210_type_info);
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type_register_static(&ehci_aw_h3_type_info);
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type_register_static(&ehci_npcm7xx_type_info);
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type_register_static(&ehci_tegra2_type_info);
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type_register_static(&ehci_ppc4xx_type_info);
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type_register_static(&ehci_fusbh200_type_info);
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@ -344,6 +344,7 @@ struct EHCIPCIState {
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#define TYPE_PLATFORM_EHCI "platform-ehci-usb"
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#define TYPE_EXYNOS4210_EHCI "exynos4210-ehci-usb"
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#define TYPE_AW_H3_EHCI "aw-h3-ehci-usb"
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#define TYPE_NPCM7XX_EHCI "npcm7xx-ehci-usb"
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#define TYPE_TEGRA2_EHCI "tegra2-ehci-usb"
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#define TYPE_PPC4xx_EHCI "ppc4xx-ehci-usb"
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#define TYPE_FUSBH200_EHCI "fusbh200-ehci-usb"
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@ -25,6 +25,8 @@
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#include "hw/nvram/npcm7xx_otp.h"
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#include "hw/timer/npcm7xx_timer.h"
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#include "hw/ssi/npcm7xx_fiu.h"
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#include "hw/usb/hcd-ehci.h"
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#include "hw/usb/hcd-ohci.h"
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#include "target/arm/cpu.h"
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#define NPCM7XX_MAX_NUM_CPUS (2)
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@ -77,6 +79,8 @@ typedef struct NPCM7xxState {
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NPCM7xxOTPState fuse_array;
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NPCM7xxMCState mc;
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NPCM7xxRNGState rng;
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EHCISysBusState ehci;
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OHCISysBusState ohci;
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NPCM7xxFIUState fiu[2];
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} NPCM7xxState;
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