Hexagon (target/hexagon) Remove gen_log_predicated_reg_write[_pair]
We assign the instruction destination register to hex_new_value[num] instead of a TCG temp that gets copied back to hex_new_value[num]. We introduce new functions get_result_gpr[_pair] to facilitate getting the proper destination register. Since we preload hex_new_value for predicated instructions, we don't need the check for slot_cancelled. So, we call gen_log_reg_write instead. We update the helper function generation and gen_tcg.h to maintain the disable-hexagon-idef-parser configuration. Here is a simple example of the differences in the TCG code generated: IN: 0x00400094: 0xf900c102 { if (P0) R2 = and(R0,R1) } BEFORE ---- 00400094 mov_i32 slot_cancelled,$0x0 mov_i32 new_r2,r2 mov_i32 loc2,$0x0 and_i32 tmp0,p0,$0x1 brcond_i32 tmp0,$0x0,eq,$L1 and_i32 tmp0,r0,r1 mov_i32 loc2,tmp0 br $L2 set_label $L1 or_i32 slot_cancelled,slot_cancelled,$0x8 set_label $L2 and_i32 tmp0,slot_cancelled,$0x8 movcond_i32 new_r2,tmp0,$0x0,loc2,new_r2,eq mov_i32 r2,new_r2 AFTER ---- 00400094 mov_i32 slot_cancelled,$0x0 mov_i32 new_r2,r2 and_i32 tmp0,p0,$0x1 brcond_i32 tmp0,$0x0,eq,$L1 and_i32 tmp0,r0,r1 mov_i32 new_r2,tmp0 br $L2 set_label $L1 or_i32 slot_cancelled,slot_cancelled,$0x8 set_label $L2 mov_i32 r2,new_r2 We'll remove the unnecessary manipulation of slot_cancelled in a subsequent patch. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230307025828.1612809-13-tsimpson@quicinc.com>
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@ -1,7 +1,7 @@
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#!/usr/bin/env python3
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##
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## Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved.
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## Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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@ -226,6 +226,14 @@ def gen_helper_function(f, tag, tagregs, tagimms):
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print("Bad register parse: ",regtype,regid,toss,numregs)
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i += 1
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## For conditional instructions, we pass in the destination register
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if 'A_CONDEXEC' in hex_common.attribdict[tag]:
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for regtype, regid, toss, numregs in regs:
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if (hex_common.is_writeonly(regid) and
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not hex_common.is_hvx_reg(regtype)):
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gen_helper_arg_opn(f, regtype, regid, i, tag)
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i += 1
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## Arguments to the helper function are the source regs and immediates
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for regtype,regid,toss,numregs in regs:
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if (hex_common.is_read(regid)):
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@ -262,10 +270,11 @@ def gen_helper_function(f, tag, tagregs, tagimms):
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if hex_common.need_ea(tag): gen_decl_ea(f)
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## Declare the return variable
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i=0
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for regtype,regid,toss,numregs in regs:
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if (hex_common.is_writeonly(regid)):
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gen_helper_dest_decl_opn(f,regtype,regid,i)
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i += 1
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if 'A_CONDEXEC' not in hex_common.attribdict[tag]:
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for regtype,regid,toss,numregs in regs:
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if (hex_common.is_writeonly(regid)):
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gen_helper_dest_decl_opn(f,regtype,regid,i)
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i += 1
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for regtype,regid,toss,numregs in regs:
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if (hex_common.is_read(regid)):
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@ -1,7 +1,7 @@
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#!/usr/bin/env python3
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##
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## Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved.
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## Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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@ -87,6 +87,7 @@ def gen_helper_prototype(f, tag, tagregs, tagimms):
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if hex_common.need_slot(tag): def_helper_size += 1
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if hex_common.need_PC(tag): def_helper_size += 1
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if hex_common.helper_needs_next_PC(tag): def_helper_size += 1
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if hex_common.need_condexec_reg(tag, regs): def_helper_size += 1
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f.write('DEF_HELPER_%s(%s' % (def_helper_size, tag))
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## The return type is void
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f.write(', void' )
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@ -96,6 +97,7 @@ def gen_helper_prototype(f, tag, tagregs, tagimms):
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if hex_common.need_part1(tag): def_helper_size += 1
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if hex_common.need_slot(tag): def_helper_size += 1
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if hex_common.need_PC(tag): def_helper_size += 1
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if hex_common.need_condexec_reg(tag, regs): def_helper_size += 1
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if hex_common.helper_needs_next_PC(tag): def_helper_size += 1
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f.write('DEF_HELPER_%s(%s' % (def_helper_size, tag))
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@ -121,6 +123,14 @@ def gen_helper_prototype(f, tag, tagregs, tagimms):
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gen_def_helper_opn(f, tag, regtype, regid, toss, numregs, i)
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i += 1
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## For conditional instructions, we pass in the destination register
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if 'A_CONDEXEC' in hex_common.attribdict[tag]:
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for regtype, regid, toss, numregs in regs:
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if (hex_common.is_writeonly(regid) and
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not hex_common.is_hvx_reg(regtype)):
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gen_def_helper_opn(f, tag, regtype, regid, toss, numregs, i)
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i += 1
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## Generate the qemu type for each input operand (regs and immediates)
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for regtype,regid,toss,numregs in regs:
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if (hex_common.is_read(regid)):
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@ -332,8 +332,6 @@
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tcg_gen_movi_tl(EA, 0); \
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PRED; \
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CHECK_NOSHUF_PRED(GET_EA, SIZE, LSB); \
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PRED_LOAD_CANCEL(LSB, EA); \
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tcg_gen_movi_tl(RdV, 0); \
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tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, label); \
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fLOAD(1, SIZE, SIGN, EA, RdV); \
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gen_set_label(label); \
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@ -391,8 +389,6 @@
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tcg_gen_movi_tl(EA, 0); \
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PRED; \
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CHECK_NOSHUF_PRED(GET_EA, 8, LSB); \
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PRED_LOAD_CANCEL(LSB, EA); \
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tcg_gen_movi_i64(RddV, 0); \
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tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, label); \
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fLOAD(1, 8, u, EA, RddV); \
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gen_set_label(label); \
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@ -504,7 +500,7 @@
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*/
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#define fGEN_TCG_SL2_return(SHORTCODE) \
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do { \
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TCGv_i64 RddV = tcg_temp_new_i64(); \
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TCGv_i64 RddV = get_result_gpr_pair(ctx, HEX_REG_FP); \
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gen_return(ctx, RddV, hex_gpr[HEX_REG_FP]); \
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gen_log_reg_write_pair(HEX_REG_FP, RddV); \
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} while (0)
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@ -30,23 +30,33 @@ def gen_decl_ea_tcg(f, tag):
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def genptr_decl_pair_writable(f, tag, regtype, regid, regno):
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regN="%s%sN" % (regtype,regid)
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f.write(" TCGv_i64 %s%sV = tcg_temp_new_i64();\n" % \
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(regtype, regid))
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if (regtype == "C"):
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if (regtype == "R"):
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f.write(" const int %s = insn->regno[%d];\n" % (regN, regno))
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elif (regtype == "C"):
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f.write(" const int %s = insn->regno[%d] + HEX_REG_SA0;\n" % \
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(regN, regno))
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else:
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f.write(" const int %s = insn->regno[%d];\n" % (regN, regno))
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print("Bad register parse: ", regtype, regid)
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f.write(" TCGv_i64 %s%sV = get_result_gpr_pair(ctx, %s);\n" % \
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(regtype, regid, regN))
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def genptr_decl_writable(f, tag, regtype, regid, regno):
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regN="%s%sN" % (regtype,regid)
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f.write(" TCGv %s%sV = tcg_temp_new();\n" % \
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(regtype, regid))
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if (regtype == "C"):
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if (regtype == "R"):
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f.write(" const int %s = insn->regno[%d];\n" % (regN, regno))
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f.write(" TCGv %s%sV = get_result_gpr(ctx, %s);\n" % \
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(regtype, regid, regN))
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elif (regtype == "C"):
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f.write(" const int %s = insn->regno[%d] + HEX_REG_SA0;\n" % \
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(regN, regno))
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else:
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f.write(" TCGv %s%sV = get_result_gpr(ctx, %s);\n" % \
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(regtype, regid, regN))
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elif (regtype == "P"):
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f.write(" const int %s = insn->regno[%d];\n" % (regN, regno))
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f.write(" TCGv %s%sV = tcg_temp_new();\n" % \
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(regtype, regid))
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else:
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print("Bad register parse: ", regtype, regid)
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def genptr_decl(f, tag, regtype, regid, regno):
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regN="%s%sN" % (regtype,regid)
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@ -249,8 +259,12 @@ def genptr_src_read(f, tag, regtype, regid):
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f.write(" hex_gpr[%s%sN + 1]);\n" % \
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(regtype, regid))
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elif (regid in {"x", "y"}):
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f.write(" tcg_gen_mov_tl(%s%sV, hex_gpr[%s%sN]);\n" % \
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(regtype,regid,regtype,regid))
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## For read/write registers, we need to get the original value into
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## the result TCGv. For conditional instructions, this is done in
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## gen_start_packet. For unconditional instructions, we do it here.
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if ('A_CONDEXEC' not in hex_common.attribdict[tag]):
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f.write(" tcg_gen_mov_tl(%s%sV, hex_gpr[%s%sN]);\n" % \
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(regtype, regid, regtype, regid))
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elif (regid not in {"s", "t", "u", "v"}):
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print("Bad register parse: ", regtype, regid)
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elif (regtype == "P"):
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@ -360,25 +374,16 @@ def gen_helper_call_imm(f,immlett):
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f.write(", tcgv_%s" % hex_common.imm_name(immlett))
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def genptr_dst_write_pair(f, tag, regtype, regid):
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if ('A_CONDEXEC' in hex_common.attribdict[tag]):
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f.write(" gen_log_predicated_reg_write_pair(%s%sN, %s%sV, insn->slot);\n" % \
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(regtype, regid, regtype, regid))
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else:
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f.write(" gen_log_reg_write_pair(%s%sN, %s%sV);\n" % \
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(regtype, regid, regtype, regid))
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f.write(" gen_log_reg_write_pair(%s%sN, %s%sV);\n" % \
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(regtype, regid, regtype, regid))
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def genptr_dst_write(f, tag, regtype, regid):
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if (regtype == "R"):
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if (regid in {"dd", "xx", "yy"}):
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genptr_dst_write_pair(f, tag, regtype, regid)
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elif (regid in {"d", "e", "x", "y"}):
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if ('A_CONDEXEC' in hex_common.attribdict[tag]):
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f.write(" gen_log_predicated_reg_write(%s%sN, %s%sV,\n" % \
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(regtype, regid, regtype, regid))
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f.write(" insn->slot);\n")
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else:
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f.write(" gen_log_reg_write(%s%sN, %s%sV);\n" % \
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(regtype, regid, regtype, regid))
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f.write(" gen_log_reg_write(%s%sN, %s%sV);\n" % \
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(regtype, regid, regtype, regid))
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else:
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print("Bad register parse: ", regtype, regid)
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elif (regtype == "P"):
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@ -462,14 +467,15 @@ def genptr_dst_write_opn(f,regtype, regid, tag):
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## For A2_add: Rd32=add(Rs32,Rt32), { RdV=RsV+RtV;}
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## We produce:
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## static void generate_A2_add(DisasContext *ctx)
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## {
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## TCGv RdV = tcg_temp_new();
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## const int RdN = insn->regno[0];
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## TCGv RsV = hex_gpr[insn->regno[1]];
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## TCGv RtV = hex_gpr[insn->regno[2]];
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## <GEN>
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## gen_log_reg_write(RdN, RdV);
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## }
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## {
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## Insn *insn __attribute__((unused)) = ctx->insn;
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## const int RdN = insn->regno[0];
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## TCGv RdV = get_result_gpr(ctx, RdN);
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## TCGv RsV = hex_gpr[insn->regno[1]];
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## TCGv RtV = hex_gpr[insn->regno[2]];
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## <GEN>
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## gen_log_reg_write(RdN, RdV);
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## }
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##
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## where <GEN> depends on hex_common.skip_qemu_helper(tag)
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## if hex_common.skip_qemu_helper(tag) is True
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@ -553,6 +559,14 @@ def gen_tcg_func(f, tag, regs, imms):
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if (i > 0): f.write(", ")
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f.write("cpu_env")
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i=1
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## For conditional instructions, we pass in the destination register
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if 'A_CONDEXEC' in hex_common.attribdict[tag]:
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for regtype, regid, toss, numregs in regs:
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if (hex_common.is_writeonly(regid) and
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not hex_common.is_hvx_reg(regtype)):
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gen_helper_call_opn(f, tag, regtype, regid, toss, \
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numregs, i)
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i += 1
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for regtype,regid,toss,numregs in regs:
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if (hex_common.is_written(regid)):
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if (not hex_common.is_hvx_reg(regtype)):
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@ -68,26 +68,17 @@ static inline void gen_masked_reg_write(TCGv new_val, TCGv cur_val,
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}
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}
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static inline void gen_log_predicated_reg_write(int rnum, TCGv val,
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uint32_t slot)
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static TCGv get_result_gpr(DisasContext *ctx, int rnum)
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{
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TCGv zero = tcg_constant_tl(0);
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TCGv slot_mask = tcg_temp_new();
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return hex_new_value[rnum];
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}
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tcg_gen_andi_tl(slot_mask, hex_slot_cancelled, 1 << slot);
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tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum], slot_mask, zero,
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val, hex_new_value[rnum]);
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if (HEX_DEBUG) {
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/*
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* Do this so HELPER(debug_commit_end) will know
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*
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* Note that slot_mask indicates the value is not written
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* (i.e., slot was cancelled), so we create a true/false value before
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* or'ing with hex_reg_written[rnum].
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*/
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tcg_gen_setcond_tl(TCG_COND_EQ, slot_mask, slot_mask, zero);
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tcg_gen_or_tl(hex_reg_written[rnum], hex_reg_written[rnum], slot_mask);
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}
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static TCGv_i64 get_result_gpr_pair(DisasContext *ctx, int rnum)
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{
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TCGv_i64 result = tcg_temp_new_i64();
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tcg_gen_concat_i32_i64(result, hex_new_value[rnum],
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hex_new_value[rnum + 1]);
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return result;
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}
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void gen_log_reg_write(int rnum, TCGv val)
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@ -102,39 +93,6 @@ void gen_log_reg_write(int rnum, TCGv val)
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}
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}
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static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val,
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uint32_t slot)
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{
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TCGv val32 = tcg_temp_new();
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TCGv zero = tcg_constant_tl(0);
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TCGv slot_mask = tcg_temp_new();
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tcg_gen_andi_tl(slot_mask, hex_slot_cancelled, 1 << slot);
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/* Low word */
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tcg_gen_extrl_i64_i32(val32, val);
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tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum],
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slot_mask, zero,
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val32, hex_new_value[rnum]);
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/* High word */
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tcg_gen_extrh_i64_i32(val32, val);
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tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum + 1],
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slot_mask, zero,
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val32, hex_new_value[rnum + 1]);
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if (HEX_DEBUG) {
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/*
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* Do this so HELPER(debug_commit_end) will know
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*
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* Note that slot_mask indicates the value is not written
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* (i.e., slot was cancelled), so we create a true/false value before
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* or'ing with hex_reg_written[rnum].
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*/
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tcg_gen_setcond_tl(TCG_COND_EQ, slot_mask, slot_mask, zero);
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tcg_gen_or_tl(hex_reg_written[rnum], hex_reg_written[rnum], slot_mask);
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tcg_gen_or_tl(hex_reg_written[rnum + 1], hex_reg_written[rnum + 1],
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slot_mask);
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}
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}
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static void gen_log_reg_write_pair(int rnum, TCGv_i64 val)
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{
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const target_ulong reg_mask_low = reg_immut_masks[rnum];
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@ -290,11 +248,12 @@ static inline void gen_write_ctrl_reg_pair(DisasContext *ctx, int reg_num,
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TCGv_i64 val)
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{
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if (reg_num == HEX_REG_P3_0_ALIASED) {
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TCGv result = get_result_gpr(ctx, reg_num + 1);
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TCGv val32 = tcg_temp_new();
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tcg_gen_extrl_i64_i32(val32, val);
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gen_write_p3_0(ctx, val32);
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tcg_gen_extrh_i64_i32(val32, val);
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gen_log_reg_write(reg_num + 1, val32);
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tcg_gen_mov_tl(result, val32);
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} else {
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gen_log_reg_write_pair(reg_num, val);
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if (reg_num == HEX_REG_QEMU_PKT_CNT) {
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@ -673,31 +632,28 @@ static void gen_jumpr(DisasContext *ctx, TCGv new_pc)
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||||
static void gen_call(DisasContext *ctx, int pc_off)
|
||||
{
|
||||
TCGv next_PC =
|
||||
tcg_constant_tl(ctx->pkt->pc + ctx->pkt->encod_pkt_size_in_bytes);
|
||||
gen_log_reg_write(HEX_REG_LR, next_PC);
|
||||
TCGv lr = get_result_gpr(ctx, HEX_REG_LR);
|
||||
tcg_gen_movi_tl(lr, ctx->next_PC);
|
||||
gen_write_new_pc_pcrel(ctx, pc_off, TCG_COND_ALWAYS, NULL);
|
||||
}
|
||||
|
||||
static void gen_callr(DisasContext *ctx, TCGv new_pc)
|
||||
{
|
||||
TCGv next_PC = tcg_constant_tl(ctx->next_PC);
|
||||
gen_log_reg_write(HEX_REG_LR, next_PC);
|
||||
TCGv lr = get_result_gpr(ctx, HEX_REG_LR);
|
||||
tcg_gen_movi_tl(lr, ctx->next_PC);
|
||||
gen_write_new_pc_addr(ctx, new_pc, TCG_COND_ALWAYS, NULL);
|
||||
}
|
||||
|
||||
static void gen_cond_call(DisasContext *ctx, TCGv pred,
|
||||
TCGCond cond, int pc_off)
|
||||
{
|
||||
TCGv next_PC;
|
||||
TCGv lr = get_result_gpr(ctx, HEX_REG_LR);
|
||||
TCGv lsb = tcg_temp_new();
|
||||
TCGLabel *skip = gen_new_label();
|
||||
tcg_gen_andi_tl(lsb, pred, 1);
|
||||
gen_write_new_pc_pcrel(ctx, pc_off, cond, lsb);
|
||||
tcg_gen_brcondi_tl(cond, lsb, 0, skip);
|
||||
next_PC =
|
||||
tcg_constant_tl(ctx->pkt->pc + ctx->pkt->encod_pkt_size_in_bytes);
|
||||
gen_log_reg_write(HEX_REG_LR, next_PC);
|
||||
tcg_gen_movi_tl(lr, ctx->next_PC);
|
||||
gen_set_label(skip);
|
||||
}
|
||||
|
||||
|
@ -728,8 +684,7 @@ static void gen_load_frame(DisasContext *ctx, TCGv_i64 frame, TCGv EA)
|
|||
tcg_gen_qemu_ld64(frame, EA, ctx->mem_idx);
|
||||
}
|
||||
|
||||
static void gen_return_base(DisasContext *ctx, TCGv_i64 dst, TCGv src,
|
||||
TCGv r29)
|
||||
static void gen_return(DisasContext *ctx, TCGv_i64 dst, TCGv src)
|
||||
{
|
||||
/*
|
||||
* frame = *src
|
||||
|
@ -739,6 +694,7 @@ static void gen_return_base(DisasContext *ctx, TCGv_i64 dst, TCGv src,
|
|||
*/
|
||||
TCGv_i64 frame = tcg_temp_new_i64();
|
||||
TCGv r31 = tcg_temp_new();
|
||||
TCGv r29 = get_result_gpr(ctx, HEX_REG_SP);
|
||||
|
||||
gen_load_frame(ctx, frame, src);
|
||||
gen_frame_unscramble(frame);
|
||||
|
@ -748,45 +704,25 @@ static void gen_return_base(DisasContext *ctx, TCGv_i64 dst, TCGv src,
|
|||
gen_jumpr(ctx, r31);
|
||||
}
|
||||
|
||||
static void gen_return(DisasContext *ctx, TCGv_i64 dst, TCGv src)
|
||||
{
|
||||
TCGv r29 = tcg_temp_new();
|
||||
gen_return_base(ctx, dst, src, r29);
|
||||
gen_log_reg_write(HEX_REG_SP, r29);
|
||||
}
|
||||
|
||||
/* if (pred) dst = dealloc_return(src):raw */
|
||||
static void gen_cond_return(DisasContext *ctx, TCGv_i64 dst, TCGv src,
|
||||
TCGv pred, TCGCond cond)
|
||||
{
|
||||
TCGv LSB = tcg_temp_new();
|
||||
TCGv mask = tcg_temp_new();
|
||||
TCGv r29 = tcg_temp_new();
|
||||
TCGLabel *skip = gen_new_label();
|
||||
tcg_gen_andi_tl(LSB, pred, 1);
|
||||
|
||||
/* Initialize the results in case the predicate is false */
|
||||
tcg_gen_movi_i64(dst, 0);
|
||||
tcg_gen_movi_tl(r29, 0);
|
||||
|
||||
/* Set the bit in hex_slot_cancelled if the predicate is flase */
|
||||
tcg_gen_movi_tl(mask, 1 << ctx->insn->slot);
|
||||
tcg_gen_or_tl(mask, hex_slot_cancelled, mask);
|
||||
tcg_gen_movcond_tl(cond, hex_slot_cancelled, LSB, tcg_constant_tl(0),
|
||||
mask, hex_slot_cancelled);
|
||||
|
||||
tcg_gen_brcondi_tl(cond, LSB, 0, skip);
|
||||
gen_return_base(ctx, dst, src, r29);
|
||||
gen_return(ctx, dst, src);
|
||||
gen_set_label(skip);
|
||||
gen_log_predicated_reg_write(HEX_REG_SP, r29, ctx->insn->slot);
|
||||
}
|
||||
|
||||
/* sub-instruction version (no RddV, so handle it manually) */
|
||||
static void gen_cond_return_subinsn(DisasContext *ctx, TCGCond cond, TCGv pred)
|
||||
{
|
||||
TCGv_i64 RddV = tcg_temp_new_i64();
|
||||
TCGv_i64 RddV = get_result_gpr_pair(ctx, HEX_REG_FP);
|
||||
gen_cond_return(ctx, RddV, hex_gpr[HEX_REG_FP], pred, cond);
|
||||
gen_log_predicated_reg_write_pair(HEX_REG_FP, RddV, ctx->insn->slot);
|
||||
gen_log_reg_write_pair(HEX_REG_FP, RddV);
|
||||
}
|
||||
|
||||
static void gen_endloop0(DisasContext *ctx)
|
||||
|
@ -836,9 +772,9 @@ static void gen_endloop0(DisasContext *ctx)
|
|||
TCGLabel *label3 = gen_new_label();
|
||||
tcg_gen_brcondi_tl(TCG_COND_LEU, hex_gpr[HEX_REG_LC0], 1, label3);
|
||||
{
|
||||
TCGv lc0 = get_result_gpr(ctx, HEX_REG_LC0);
|
||||
gen_jumpr(ctx, hex_gpr[HEX_REG_SA0]);
|
||||
tcg_gen_subi_tl(hex_new_value[HEX_REG_LC0],
|
||||
hex_gpr[HEX_REG_LC0], 1);
|
||||
tcg_gen_subi_tl(lc0, hex_gpr[HEX_REG_LC0], 1);
|
||||
}
|
||||
gen_set_label(label3);
|
||||
}
|
||||
|
@ -855,8 +791,9 @@ static void gen_endloop1(DisasContext *ctx)
|
|||
TCGLabel *label = gen_new_label();
|
||||
tcg_gen_brcondi_tl(TCG_COND_LEU, hex_gpr[HEX_REG_LC1], 1, label);
|
||||
{
|
||||
TCGv lc1 = get_result_gpr(ctx, HEX_REG_LC1);
|
||||
gen_jumpr(ctx, hex_gpr[HEX_REG_SA1]);
|
||||
tcg_gen_subi_tl(hex_new_value[HEX_REG_LC1], hex_gpr[HEX_REG_LC1], 1);
|
||||
tcg_gen_subi_tl(lc1, hex_gpr[HEX_REG_LC1], 1);
|
||||
}
|
||||
gen_set_label(label);
|
||||
}
|
||||
|
@ -909,15 +846,17 @@ static void gen_endloop01(DisasContext *ctx)
|
|||
*/
|
||||
tcg_gen_brcondi_tl(TCG_COND_LEU, hex_gpr[HEX_REG_LC0], 1, label3);
|
||||
{
|
||||
TCGv lc0 = get_result_gpr(ctx, HEX_REG_LC0);
|
||||
gen_jumpr(ctx, hex_gpr[HEX_REG_SA0]);
|
||||
tcg_gen_subi_tl(hex_new_value[HEX_REG_LC0], hex_gpr[HEX_REG_LC0], 1);
|
||||
tcg_gen_subi_tl(lc0, hex_gpr[HEX_REG_LC0], 1);
|
||||
tcg_gen_br(done);
|
||||
}
|
||||
gen_set_label(label3);
|
||||
tcg_gen_brcondi_tl(TCG_COND_LEU, hex_gpr[HEX_REG_LC1], 1, done);
|
||||
{
|
||||
TCGv lc1 = get_result_gpr(ctx, HEX_REG_LC1);
|
||||
gen_jumpr(ctx, hex_gpr[HEX_REG_SA1]);
|
||||
tcg_gen_subi_tl(hex_new_value[HEX_REG_LC1], hex_gpr[HEX_REG_LC1], 1);
|
||||
tcg_gen_subi_tl(lc1, hex_gpr[HEX_REG_LC1], 1);
|
||||
}
|
||||
gen_set_label(done);
|
||||
}
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
#!/usr/bin/env python3
|
||||
|
||||
##
|
||||
## Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved.
|
||||
## Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
|
@ -237,6 +237,13 @@ def helper_needs_next_PC(tag):
|
|||
def need_pkt_has_multi_cof(tag):
|
||||
return 'A_COF' in attribdict[tag]
|
||||
|
||||
def need_condexec_reg(tag, regs):
|
||||
if 'A_CONDEXEC' in attribdict[tag]:
|
||||
for regtype, regid, toss, numregs in regs:
|
||||
if is_writeonly(regid) and not is_hvx_reg(regtype):
|
||||
return True
|
||||
return False
|
||||
|
||||
def skip_qemu_helper(tag):
|
||||
return tag in overrides.keys()
|
||||
|
||||
|
|
|
@ -1668,9 +1668,7 @@ void gen_inst_init_args(Context *c, YYLTYPE *locp)
|
|||
for (unsigned i = 0; i < c->inst.init_list->len; i++) {
|
||||
HexValue *val = &g_array_index(c->inst.init_list, HexValue, i);
|
||||
if (val->type == REGISTER_ARG) {
|
||||
char reg_id[5];
|
||||
reg_compose(c, locp, &val->reg, reg_id);
|
||||
EMIT_HEAD(c, "tcg_gen_movi_i%u(%s, 0);\n", val->bit_width, reg_id);
|
||||
/* Nothing to do here */
|
||||
} else if (val->type == PREDICATE) {
|
||||
char suffix = val->is_dotnew ? 'N' : 'V';
|
||||
EMIT_HEAD(c, "tcg_gen_movi_i%u(P%c%c, 0);\n", val->bit_width,
|
||||
|
|
|
@ -210,21 +210,6 @@ static inline void gen_cancel(uint32_t slot)
|
|||
|
||||
#define LOAD_CANCEL(EA) do { CANCEL; } while (0)
|
||||
|
||||
#ifdef QEMU_GENERATE
|
||||
static inline void gen_pred_cancel(TCGv pred, uint32_t slot_num)
|
||||
{
|
||||
TCGv slot_mask = tcg_temp_new();
|
||||
TCGv tmp = tcg_temp_new();
|
||||
TCGv zero = tcg_constant_tl(0);
|
||||
tcg_gen_ori_tl(slot_mask, hex_slot_cancelled, 1 << slot_num);
|
||||
tcg_gen_andi_tl(tmp, pred, 1);
|
||||
tcg_gen_movcond_tl(TCG_COND_EQ, hex_slot_cancelled, tmp, zero,
|
||||
slot_mask, hex_slot_cancelled);
|
||||
}
|
||||
#define PRED_LOAD_CANCEL(PRED, EA) \
|
||||
gen_pred_cancel(PRED, insn->is_endloop ? 4 : insn->slot)
|
||||
#endif
|
||||
|
||||
#define STORE_CANCEL(EA) { env->slot_cancelled |= (1 << slot); }
|
||||
|
||||
#define fMAX(A, B) (((A) > (B)) ? (A) : (B))
|
||||
|
|
Loading…
Reference in New Issue