From e2c3fb069994858fea9aca9a4e64fa5afd34021a Mon Sep 17 00:00:00 2001 From: David Miller Date: Wed, 23 Feb 2022 17:31:16 -0500 Subject: [PATCH] tests/tcg/s390x: Tests for Miscellaneous-Instruction-Extensions Facility 3 tests/tcg/s390x/mie3-compl.c: [N]*K instructions tests/tcg/s390x/mie3-mvcrl.c: MVCRL instruction tests/tcg/s390x/mie3-sel.c: SELECT instruction Signed-off-by: David Miller Message-Id: <20220223223117.66660-4-dmiller423@gmail.com> [thuth: Squash mnemonic -> .insn patch, white space cleanup, improve asm usage] Signed-off-by: Thomas Huth --- tests/tcg/s390x/Makefile.target | 3 +++ tests/tcg/s390x/mie3-compl.c | 48 +++++++++++++++++++++++++++++++++ tests/tcg/s390x/mie3-mvcrl.c | 27 +++++++++++++++++++ tests/tcg/s390x/mie3-sel.c | 38 ++++++++++++++++++++++++++ 4 files changed, 116 insertions(+) create mode 100644 tests/tcg/s390x/mie3-compl.c create mode 100644 tests/tcg/s390x/mie3-mvcrl.c create mode 100644 tests/tcg/s390x/mie3-sel.c diff --git a/tests/tcg/s390x/Makefile.target b/tests/tcg/s390x/Makefile.target index 1a7238b4eb..8c9b6a13ce 100644 --- a/tests/tcg/s390x/Makefile.target +++ b/tests/tcg/s390x/Makefile.target @@ -7,6 +7,9 @@ TESTS+=ipm TESTS+=exrl-trt TESTS+=exrl-trtr TESTS+=pack +TESTS+=mie3-compl +TESTS+=mie3-mvcrl +TESTS+=mie3-sel TESTS+=mvo TESTS+=mvc TESTS+=shift diff --git a/tests/tcg/s390x/mie3-compl.c b/tests/tcg/s390x/mie3-compl.c new file mode 100644 index 0000000000..35649f3b02 --- /dev/null +++ b/tests/tcg/s390x/mie3-compl.c @@ -0,0 +1,48 @@ +#include + +#define FbinOp(S, ASM) uint64_t S(uint64_t a, uint64_t b) \ +{ \ + uint64_t res = 0; \ + asm ("llihf %[res],801\n" ASM \ + : [res]"=&r"(res) : [a]"r"(a), [b]"r"(b) : "cc"); \ + return res; \ +} + +/* AND WITH COMPLEMENT */ +FbinOp(_ncrk, ".insn rrf, 0xB9F50000, %[res], %[b], %[a], 0\n") +FbinOp(_ncgrk, ".insn rrf, 0xB9E50000, %[res], %[b], %[a], 0\n") + +/* NAND */ +FbinOp(_nnrk, ".insn rrf, 0xB9740000, %[res], %[b], %[a], 0\n") +FbinOp(_nngrk, ".insn rrf, 0xB9640000, %[res], %[b], %[a], 0\n") + +/* NOT XOR */ +FbinOp(_nxrk, ".insn rrf, 0xB9770000, %[res], %[b], %[a], 0\n") +FbinOp(_nxgrk, ".insn rrf, 0xB9670000, %[res], %[b], %[a], 0\n") + +/* NOR */ +FbinOp(_nork, ".insn rrf, 0xB9760000, %[res], %[b], %[a], 0\n") +FbinOp(_nogrk, ".insn rrf, 0xB9660000, %[res], %[b], %[a], 0\n") + +/* OR WITH COMPLEMENT */ +FbinOp(_ocrk, ".insn rrf, 0xB9750000, %[res], %[b], %[a], 0\n") +FbinOp(_ocgrk, ".insn rrf, 0xB9650000, %[res], %[b], %[a], 0\n") + +int main(int argc, char *argv[]) +{ + if (_ncrk(0xFF88, 0xAA11) != 0x0000032100000011ull || + _nnrk(0xFF88, 0xAA11) != 0x00000321FFFF55FFull || + _nork(0xFF88, 0xAA11) != 0x00000321FFFF0066ull || + _nxrk(0xFF88, 0xAA11) != 0x00000321FFFFAA66ull || + _ocrk(0xFF88, 0xAA11) != 0x00000321FFFFAA77ull || + _ncgrk(0xFF88, 0xAA11) != 0x0000000000000011ull || + _nngrk(0xFF88, 0xAA11) != 0xFFFFFFFFFFFF55FFull || + _nogrk(0xFF88, 0xAA11) != 0xFFFFFFFFFFFF0066ull || + _nxgrk(0xFF88, 0xAA11) != 0xFFFFFFFFFFFFAA66ull || + _ocgrk(0xFF88, 0xAA11) != 0xFFFFFFFFFFFFAA77ull) + { + return 1; + } + + return 0; +} diff --git a/tests/tcg/s390x/mie3-mvcrl.c b/tests/tcg/s390x/mie3-mvcrl.c new file mode 100644 index 0000000000..57b08e48d0 --- /dev/null +++ b/tests/tcg/s390x/mie3-mvcrl.c @@ -0,0 +1,27 @@ +#include +#include + +static inline void mvcrl_8(const char *dst, const char *src) +{ + asm volatile ( + "llill %%r0, 8\n" + ".insn sse, 0xE50A00000000, 0(%[dst]), 0(%[src])" + : : [dst] "d" (dst), [src] "d" (src) + : "memory"); +} + +int main(int argc, char *argv[]) +{ + const char *alpha = "abcdefghijklmnop"; + + /* array missing 'i' */ + char tstr[17] = "abcdefghjklmnop\0" ; + + /* mvcrl reference use: 'open a hole in an array' */ + mvcrl_8(tstr + 9, tstr + 8); + + /* place missing 'i' */ + tstr[8] = 'i'; + + return strncmp(alpha, tstr, 16ul); +} diff --git a/tests/tcg/s390x/mie3-sel.c b/tests/tcg/s390x/mie3-sel.c new file mode 100644 index 0000000000..b0c5c9857d --- /dev/null +++ b/tests/tcg/s390x/mie3-sel.c @@ -0,0 +1,38 @@ +#include + +#define Fi3(S, ASM) uint64_t S(uint64_t a, uint64_t b, uint64_t c) \ +{ \ + uint64_t res = 0; \ + asm ( \ + "lg %%r2, %[a]\n" \ + "lg %%r3, %[b]\n" \ + "lg %%r0, %[c]\n" \ + "ltgr %%r0, %%r0\n" \ + ASM \ + "stg %%r0, %[res] " \ + : [res] "=m" (res) \ + : [a] "m" (a), \ + [b] "m" (b), \ + [c] "m" (c) \ + : "r0", "r2", \ + "r3", "r4" \ + ); \ + return res; \ +} + +Fi3 (_selre, ".insn rrf, 0xB9F00000, %%r0, %%r3, %%r2, 8\n") +Fi3 (_selgrz, ".insn rrf, 0xB9E30000, %%r0, %%r3, %%r2, 8\n") +Fi3 (_selfhrnz, ".insn rrf, 0xB9C00000, %%r0, %%r3, %%r2, 7\n") + +int main(int argc, char *argv[]) +{ + uint64_t a = ~0, b = ~0, c = ~0; + a = _selre(0x066600000066ull, 0x066600000006ull, a); + b = _selgrz(0xF00D00000005ull, 0xF00D00000055ull, b); + c = _selfhrnz(0x043200000044ull, 0x065400000004ull, c); + + return (int) ( + (0xFFFFFFFF00000066ull != a) || + (0x0000F00D00000005ull != b) || + (0x00000654FFFFFFFFull != c)); +}