MIPS queue August 2018 v6
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABAgAGBQJbgCm7AAoJENSXKoln91plhJYH/jRqbCaUd04nGuyjOaYUajTL brz3JD0XN2jD6NnDYUpuiNzawSojNzSklMA0u9AJiG+cpNK+gqW4fX+CYeX7ApjK 99+SXSejxnK3IJUNblQDD/hdCv9Dc1r12R7c80lm+aqJwi4C8hfULTbfrse/QdyA KIHKl+c3uaWTPG2qC3mpPW/QS+IRPgRRwF/7GILuiagNmMcXyuMd2fQuePnf1rvD ztTdtNJ0zfdFK1jlLa7D9Xe36RpS1uBinF429dNwXWM/+i1shvxc3Enzb4qEQNYe ZeVxTomP/nO1elLZYdVUwdQYr6vmnvb1/mtTT6nq0NvHeLGjMZMqOBWGuAtdXoo= =a8Jv -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-aug-2018' into staging MIPS queue August 2018 v6 # gpg: Signature made Fri 24 Aug 2018 16:52:27 BST # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-aug-2018: (45 commits) target/mips: Add definition of nanoMIPS I7200 CPU mips_malta: Fix semihosting argument passing for nanoMIPS bare metal mips_malta: Add setting up GT64120 BARs to the nanoMIPS bootloader mips_malta: Add basic nanoMIPS boot code for Malta board elf: Don't check FCR31_NAN2008 bit for nanoMIPS elf: On elf loading, treat both EM_MIPS and EM_NANOMIPS as legal for MIPS elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too elf: Add EM_NANOMIPS value as a valid one for e_machine field target/mips: Fix ERET/ERETNC behavior related to ADEL exception target/mips: Add updating BadInstr and BadInstrX for nanoMIPS target/mips: Add availability control via bit NMS target/mips: Add emulation of DSP ASE for nanoMIPS - part 6 target/mips: Add emulation of DSP ASE for nanoMIPS - part 5 target/mips: Add emulation of DSP ASE for nanoMIPS - part 4 target/mips: Add emulation of DSP ASE for nanoMIPS - part 3 target/mips: Add emulation of DSP ASE for nanoMIPS - part 2 target/mips: Add emulation of DSP ASE for nanoMIPS - part 1 target/mips: Implement MT ASE support for nanoMIPS target/mips: Fix pre-nanoMIPS MT ASE instructions availability control target/mips: Add emulation of nanoMIPS 32-bit branch instructions ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
e2e6fa6793
@ -599,6 +599,208 @@ static void network_init(PCIBus *pci_bus)
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}
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}
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static void write_bootloader_nanomips(uint8_t *base, int64_t run_addr,
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int64_t kernel_entry)
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{
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uint16_t *p;
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/* Small bootloader */
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p = (uint16_t *)base;
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#define NM_HI1(VAL) (((VAL) >> 16) & 0x1f)
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#define NM_HI2(VAL) \
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(((VAL) & 0xf000) | (((VAL) >> 19) & 0xffc) | (((VAL) >> 31) & 0x1))
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#define NM_LO(VAL) ((VAL) & 0xfff)
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stw_p(p++, 0x2800); stw_p(p++, 0x001c);
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/* bc to_here */
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stw_p(p++, 0x8000); stw_p(p++, 0xc000);
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/* nop */
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stw_p(p++, 0x8000); stw_p(p++, 0xc000);
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/* nop */
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stw_p(p++, 0x8000); stw_p(p++, 0xc000);
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/* nop */
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stw_p(p++, 0x8000); stw_p(p++, 0xc000);
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/* nop */
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stw_p(p++, 0x8000); stw_p(p++, 0xc000);
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/* nop */
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stw_p(p++, 0x8000); stw_p(p++, 0xc000);
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/* nop */
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stw_p(p++, 0x8000); stw_p(p++, 0xc000);
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/* nop */
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/* to_here: */
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if (semihosting_get_argc()) {
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/* Preserve a0 content as arguments have been passed */
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stw_p(p++, 0x8000); stw_p(p++, 0xc000);
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/* nop */
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} else {
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stw_p(p++, 0x0080); stw_p(p++, 0x0002);
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/* li a0,2 */
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}
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stw_p(p++, 0xe3a0 | NM_HI1(ENVP_ADDR - 64));
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stw_p(p++, NM_HI2(ENVP_ADDR - 64));
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/* lui sp,%hi(ENVP_ADDR - 64) */
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stw_p(p++, 0x83bd); stw_p(p++, NM_LO(ENVP_ADDR - 64));
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/* ori sp,sp,%lo(ENVP_ADDR - 64) */
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stw_p(p++, 0xe0a0 | NM_HI1(ENVP_ADDR));
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stw_p(p++, NM_HI2(ENVP_ADDR));
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/* lui a1,%hi(ENVP_ADDR) */
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stw_p(p++, 0x80a5); stw_p(p++, NM_LO(ENVP_ADDR));
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/* ori a1,a1,%lo(ENVP_ADDR) */
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stw_p(p++, 0xe0c0 | NM_HI1(ENVP_ADDR + 8));
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stw_p(p++, NM_HI2(ENVP_ADDR + 8));
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/* lui a2,%hi(ENVP_ADDR + 8) */
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stw_p(p++, 0x80c6); stw_p(p++, NM_LO(ENVP_ADDR + 8));
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/* ori a2,a2,%lo(ENVP_ADDR + 8) */
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stw_p(p++, 0xe0e0 | NM_HI1(loaderparams.ram_low_size));
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stw_p(p++, NM_HI2(loaderparams.ram_low_size));
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/* lui a3,%hi(loaderparams.ram_low_size) */
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stw_p(p++, 0x80e7); stw_p(p++, NM_LO(loaderparams.ram_low_size));
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/* ori a3,a3,%lo(loaderparams.ram_low_size) */
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/*
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* Load BAR registers as done by YAMON:
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*
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* - set up PCI0 I/O BARs from 0x18000000 to 0x181fffff
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* - set up PCI0 MEM0 at 0x10000000, size 0x8000000
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* - set up PCI0 MEM1 at 0x18200000, size 0xbe00000
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*
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*/
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stw_p(p++, 0xe040); stw_p(p++, 0x0681);
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/* lui t1, %hi(0xb4000000) */
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#ifdef TARGET_WORDS_BIGENDIAN
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stw_p(p++, 0xe020); stw_p(p++, 0x0be1);
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/* lui t0, %hi(0xdf000000) */
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/* 0x68 corresponds to GT_ISD (from hw/mips/gt64xxx_pci.c) */
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stw_p(p++, 0x8422); stw_p(p++, 0x9068);
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/* sw t0, 0x68(t1) */
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stw_p(p++, 0xe040); stw_p(p++, 0x077d);
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/* lui t1, %hi(0xbbe00000) */
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stw_p(p++, 0xe020); stw_p(p++, 0x0801);
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/* lui t0, %hi(0xc0000000) */
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/* 0x48 corresponds to GT_PCI0IOLD */
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stw_p(p++, 0x8422); stw_p(p++, 0x9048);
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/* sw t0, 0x48(t1) */
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stw_p(p++, 0xe020); stw_p(p++, 0x0800);
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/* lui t0, %hi(0x40000000) */
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/* 0x50 corresponds to GT_PCI0IOHD */
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stw_p(p++, 0x8422); stw_p(p++, 0x9050);
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/* sw t0, 0x50(t1) */
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stw_p(p++, 0xe020); stw_p(p++, 0x0001);
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/* lui t0, %hi(0x80000000) */
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/* 0x58 corresponds to GT_PCI0M0LD */
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stw_p(p++, 0x8422); stw_p(p++, 0x9058);
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/* sw t0, 0x58(t1) */
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stw_p(p++, 0xe020); stw_p(p++, 0x07e0);
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/* lui t0, %hi(0x3f000000) */
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/* 0x60 corresponds to GT_PCI0M0HD */
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stw_p(p++, 0x8422); stw_p(p++, 0x9060);
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/* sw t0, 0x60(t1) */
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stw_p(p++, 0xe020); stw_p(p++, 0x0821);
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/* lui t0, %hi(0xc1000000) */
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/* 0x80 corresponds to GT_PCI0M1LD */
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stw_p(p++, 0x8422); stw_p(p++, 0x9080);
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/* sw t0, 0x80(t1) */
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stw_p(p++, 0xe020); stw_p(p++, 0x0bc0);
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/* lui t0, %hi(0x5e000000) */
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#else
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stw_p(p++, 0x0020); stw_p(p++, 0x00df);
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/* addiu[32] t0, $0, 0xdf */
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/* 0x68 corresponds to GT_ISD */
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stw_p(p++, 0x8422); stw_p(p++, 0x9068);
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/* sw t0, 0x68(t1) */
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/* Use kseg2 remapped address 0x1be00000 */
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stw_p(p++, 0xe040); stw_p(p++, 0x077d);
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/* lui t1, %hi(0xbbe00000) */
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stw_p(p++, 0x0020); stw_p(p++, 0x00c0);
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/* addiu[32] t0, $0, 0xc0 */
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/* 0x48 corresponds to GT_PCI0IOLD */
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stw_p(p++, 0x8422); stw_p(p++, 0x9048);
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/* sw t0, 0x48(t1) */
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stw_p(p++, 0x0020); stw_p(p++, 0x0040);
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/* addiu[32] t0, $0, 0x40 */
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/* 0x50 corresponds to GT_PCI0IOHD */
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stw_p(p++, 0x8422); stw_p(p++, 0x9050);
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/* sw t0, 0x50(t1) */
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stw_p(p++, 0x0020); stw_p(p++, 0x0080);
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/* addiu[32] t0, $0, 0x80 */
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/* 0x58 corresponds to GT_PCI0M0LD */
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stw_p(p++, 0x8422); stw_p(p++, 0x9058);
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/* sw t0, 0x58(t1) */
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stw_p(p++, 0x0020); stw_p(p++, 0x003f);
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/* addiu[32] t0, $0, 0x3f */
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/* 0x60 corresponds to GT_PCI0M0HD */
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stw_p(p++, 0x8422); stw_p(p++, 0x9060);
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/* sw t0, 0x60(t1) */
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stw_p(p++, 0x0020); stw_p(p++, 0x00c1);
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/* addiu[32] t0, $0, 0xc1 */
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/* 0x80 corresponds to GT_PCI0M1LD */
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stw_p(p++, 0x8422); stw_p(p++, 0x9080);
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/* sw t0, 0x80(t1) */
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stw_p(p++, 0x0020); stw_p(p++, 0x005e);
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/* addiu[32] t0, $0, 0x5e */
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#endif
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/* 0x88 corresponds to GT_PCI0M1HD */
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stw_p(p++, 0x8422); stw_p(p++, 0x9088);
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/* sw t0, 0x88(t1) */
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stw_p(p++, 0xe320 | NM_HI1(kernel_entry));
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stw_p(p++, NM_HI2(kernel_entry));
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/* lui t9,%hi(kernel_entry) */
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stw_p(p++, 0x8339); stw_p(p++, NM_LO(kernel_entry));
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/* ori t9,t9,%lo(kernel_entry) */
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stw_p(p++, 0x4bf9); stw_p(p++, 0x0000);
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/* jalrc t8 */
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}
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/* ROM and pseudo bootloader
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The following code implements a very very simple bootloader. It first
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@ -620,7 +822,6 @@ static void network_init(PCIBus *pci_bus)
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a2 - 32-bit address of the environment variables table
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a3 - RAM size in bytes
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*/
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static void write_bootloader(uint8_t *base, int64_t run_addr,
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int64_t kernel_entry)
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{
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@ -1096,8 +1297,13 @@ void mips_malta_init(MachineState *machine)
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loaderparams.initrd_filename = initrd_filename;
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kernel_entry = load_kernel();
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write_bootloader(memory_region_get_ram_ptr(bios),
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bootloader_run_addr, kernel_entry);
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if (!cpu_supports_isa(machine->cpu_type, ISA_NANOMIPS32)) {
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write_bootloader(memory_region_get_ram_ptr(bios),
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bootloader_run_addr, kernel_entry);
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} else {
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write_bootloader_nanomips(memory_region_get_ram_ptr(bios),
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bootloader_run_addr, kernel_entry);
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}
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if (kvm_enabled()) {
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/* Write the bootloader code @ the end of RAM, 1MB reserved */
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write_bootloader(memory_region_get_ram_ptr(ram_low_preio) +
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@ -143,6 +143,8 @@ typedef int64_t Elf64_Sxword;
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#define EM_RISCV 243 /* RISC-V */
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#define EM_NANOMIPS 249 /* Wave Computing nanoMIPS */
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/*
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* This is an interim value that we will use until the committee comes
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* up with a final number.
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@ -327,6 +327,14 @@ static int glue(load_elf, SZ)(const char *name, int fd,
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}
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}
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break;
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case EM_MIPS:
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case EM_NANOMIPS:
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if ((ehdr.e_machine != EM_MIPS) &&
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(ehdr.e_machine != EM_NANOMIPS)) {
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ret = ELF_LOAD_WRONG_ARCH;
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goto fail;
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}
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break;
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default:
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if (elf_machine != ehdr.e_machine) {
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ret = ELF_LOAD_WRONG_ARCH;
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@ -853,6 +853,8 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUPPCState *en
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#endif
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#define ELF_ARCH EM_MIPS
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#define elf_check_arch(x) ((x) == EM_MIPS || (x) == EM_NANOMIPS)
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static inline void init_thread(struct target_pt_regs *regs,
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struct image_info *infop)
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{
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@ -397,10 +397,13 @@ static int do_store_exclusive(CPUMIPSState *env)
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target_ulong addr;
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target_ulong page_addr;
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target_ulong val;
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uint32_t val_wp = 0;
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uint32_t llnewval_wp = 0;
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int flags;
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int segv = 0;
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int reg;
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int d;
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int wp;
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addr = env->lladdr;
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page_addr = addr & TARGET_PAGE_MASK;
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@ -412,19 +415,31 @@ static int do_store_exclusive(CPUMIPSState *env)
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} else {
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reg = env->llreg & 0x1f;
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d = (env->llreg & 0x20) != 0;
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if (d) {
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segv = get_user_s64(val, addr);
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wp = (env->llreg & 0x40) != 0;
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if (!wp) {
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if (d) {
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segv = get_user_s64(val, addr);
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} else {
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segv = get_user_s32(val, addr);
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}
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} else {
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segv = get_user_s32(val, addr);
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segv |= get_user_s32(val_wp, addr);
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llnewval_wp = env->llnewval_wp;
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}
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if (!segv) {
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if (val != env->llval) {
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if (val != env->llval && val_wp == llnewval_wp) {
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env->active_tc.gpr[reg] = 0;
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} else {
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if (d) {
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segv = put_user_u64(env->llnewval, addr);
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if (!wp) {
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if (d) {
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segv = put_user_u64(env->llnewval, addr);
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} else {
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segv = put_user_u32(env->llnewval, addr);
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}
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} else {
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segv = put_user_u32(env->llnewval, addr);
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segv |= put_user_u32(env->llnewval_wp, addr + 4);
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}
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if (!segv) {
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env->active_tc.gpr[reg] = 1;
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@ -732,6 +747,9 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
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if (regs->cp0_epc & 1) {
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env->hflags |= MIPS_HFLAG_M16;
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}
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if (env->insn_flags & ISA_NANOMIPS32) {
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return;
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}
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if (((info->elf_flags & EF_MIPS_NAN2008) != 0) !=
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((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0)) {
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if ((env->active_fpu.fcr31_rw_bitmask &
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@ -506,6 +506,8 @@ struct CPUMIPSState {
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uint64_t lladdr;
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target_ulong llval;
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target_ulong llnewval;
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uint64_t llval_wp;
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uint32_t llnewval_wp;
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target_ulong llreg;
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uint64_t CP0_LLAddr_rw_bitmask;
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int CP0_LLAddr_shift;
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@ -682,6 +682,22 @@ static void set_hflags_for_handler (CPUMIPSState *env)
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static inline void set_badinstr_registers(CPUMIPSState *env)
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{
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if (env->insn_flags & ISA_NANOMIPS32) {
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if (env->CP0_Config3 & (1 << CP0C3_BI)) {
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uint32_t instr = (cpu_lduw_code(env, env->active_tc.PC)) << 16;
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if ((instr & 0x10000000) == 0) {
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instr |= cpu_lduw_code(env, env->active_tc.PC + 2);
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}
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env->CP0_BadInstr = instr;
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if ((instr & 0xFC000000) == 0x60000000) {
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instr = cpu_lduw_code(env, env->active_tc.PC + 4) << 16;
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env->CP0_BadInstrX = instr;
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}
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}
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return;
|
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}
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|
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if (env->hflags & MIPS_HFLAG_M16) {
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/* TODO: add BadInstr support for microMIPS */
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return;
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@ -40,6 +40,8 @@ DEF_HELPER_FLAGS_1(bitswap, TCG_CALL_NO_RWG_SE, tl, tl)
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DEF_HELPER_FLAGS_1(dbitswap, TCG_CALL_NO_RWG_SE, tl, tl)
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#endif
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|
||||
DEF_HELPER_FLAGS_4(rotx, TCG_CALL_NO_RWG_SE, tl, tl, i32, i32, i32)
|
||||
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
/* CP0 helpers */
|
||||
DEF_HELPER_1(mfc0_mvpcontrol, tl, env)
|
||||
|
||||
@ -39,6 +39,7 @@
|
||||
#define ISA_MIPS64R5 0x00001000
|
||||
#define ISA_MIPS32R6 0x00002000
|
||||
#define ISA_MIPS64R6 0x00004000
|
||||
#define ISA_NANOMIPS32 0x00008000
|
||||
|
||||
/* MIPS ASEs. */
|
||||
#define ASE_MIPS16 0x00010000
|
||||
@ -87,6 +88,9 @@
|
||||
#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6)
|
||||
#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6)
|
||||
|
||||
/* Wave Computing: "nanoMIPS" */
|
||||
#define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32)
|
||||
|
||||
/* Strictly follow the architecture standard:
|
||||
- Disallow "special" instruction handling for PMON/SPIM.
|
||||
Note that we still maintain Count/Compare to match the host clock. */
|
||||
|
||||
@ -249,6 +249,100 @@ target_ulong helper_bitswap(target_ulong rt)
|
||||
return (int32_t)bitswap(rt);
|
||||
}
|
||||
|
||||
target_ulong helper_rotx(target_ulong rs, uint32_t shift, uint32_t shiftx,
|
||||
uint32_t stripe)
|
||||
{
|
||||
int i;
|
||||
uint64_t tmp0 = ((uint64_t)rs) << 32 | ((uint64_t)rs & 0xffffffff);
|
||||
uint64_t tmp1 = tmp0;
|
||||
for (i = 0; i <= 46; i++) {
|
||||
int s;
|
||||
if (i & 0x8) {
|
||||
s = shift;
|
||||
} else {
|
||||
s = shiftx;
|
||||
}
|
||||
|
||||
if (stripe != 0 && !(i & 0x4)) {
|
||||
s = ~s;
|
||||
}
|
||||
if (s & 0x10) {
|
||||
if (tmp0 & (1LL << (i + 16))) {
|
||||
tmp1 |= 1LL << i;
|
||||
} else {
|
||||
tmp1 &= ~(1LL << i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
uint64_t tmp2 = tmp1;
|
||||
for (i = 0; i <= 38; i++) {
|
||||
int s;
|
||||
if (i & 0x4) {
|
||||
s = shift;
|
||||
} else {
|
||||
s = shiftx;
|
||||
}
|
||||
|
||||
if (s & 0x8) {
|
||||
if (tmp1 & (1LL << (i + 8))) {
|
||||
tmp2 |= 1LL << i;
|
||||
} else {
|
||||
tmp2 &= ~(1LL << i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
uint64_t tmp3 = tmp2;
|
||||
for (i = 0; i <= 34; i++) {
|
||||
int s;
|
||||
if (i & 0x2) {
|
||||
s = shift;
|
||||
} else {
|
||||
s = shiftx;
|
||||
}
|
||||
if (s & 0x4) {
|
||||
if (tmp2 & (1LL << (i + 4))) {
|
||||
tmp3 |= 1LL << i;
|
||||
} else {
|
||||
tmp3 &= ~(1LL << i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
uint64_t tmp4 = tmp3;
|
||||
for (i = 0; i <= 32; i++) {
|
||||
int s;
|
||||
if (i & 0x1) {
|
||||
s = shift;
|
||||
} else {
|
||||
s = shiftx;
|
||||
}
|
||||
if (s & 0x2) {
|
||||
if (tmp3 & (1LL << (i + 2))) {
|
||||
tmp4 |= 1LL << i;
|
||||
} else {
|
||||
tmp4 &= ~(1LL << i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
uint64_t tmp5 = tmp4;
|
||||
for (i = 0; i <= 31; i++) {
|
||||
int s;
|
||||
s = shift;
|
||||
if (s & 0x1) {
|
||||
if (tmp4 & (1LL << (i + 1))) {
|
||||
tmp5 |= 1LL << i;
|
||||
} else {
|
||||
tmp5 &= ~(1LL << i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return (int64_t)(int32_t)(uint32_t)tmp5;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
|
||||
static inline hwaddr do_translate_address(CPUMIPSState *env,
|
||||
@ -2333,10 +2427,12 @@ void helper_eretnc(CPUMIPSState *env)
|
||||
void helper_deret(CPUMIPSState *env)
|
||||
{
|
||||
debug_pre_eret(env);
|
||||
set_pc(env, env->CP0_DEPC);
|
||||
|
||||
env->hflags &= ~MIPS_HFLAG_DM;
|
||||
compute_hflags(env);
|
||||
|
||||
set_pc(env, env->CP0_DEPC);
|
||||
|
||||
debug_post_eret(env);
|
||||
}
|
||||
#endif /* !CONFIG_USER_ONLY */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -449,6 +449,45 @@ const mips_def_t mips_defs[] =
|
||||
.insn_flags = CPU_MIPS32R6 | ASE_MICROMIPS,
|
||||
.mmu_type = MMU_TYPE_R4000,
|
||||
},
|
||||
{
|
||||
.name = "I7200",
|
||||
.CP0_PRid = 0x00010000,
|
||||
.CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (0x2 << CP0C0_AR) |
|
||||
(MMU_TYPE_R4000 << CP0C0_MT),
|
||||
.CP0_Config1 = (1U << CP0C1_M) | (15 << CP0C1_MMU) | (2 << CP0C1_IS) |
|
||||
(4 << CP0C1_IL) | (3 << CP0C1_IA) | (2 << CP0C1_DS) |
|
||||
(4 << CP0C1_DL) | (3 << CP0C1_DA) | (1 << CP0C1_PC) |
|
||||
(1 << CP0C1_EP),
|
||||
.CP0_Config2 = MIPS_CONFIG2,
|
||||
.CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_CMGCR) |
|
||||
(1 << CP0C3_BI) | (1 << CP0C3_SC) | (3 << CP0C3_MMAR) |
|
||||
(1 << CP0C3_ISA_ON_EXC) | (1 << CP0C3_ISA) |
|
||||
(1 << CP0C3_ULRI) | (1 << CP0C3_RXI) |
|
||||
(1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) |
|
||||
(1 << CP0C3_CTXTC) | (1 << CP0C3_VInt) |
|
||||
(1 << CP0C3_CDMM) | (1 << CP0C3_MT) | (1 << CP0C3_TL),
|
||||
.CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
|
||||
(2 << CP0C4_IE) | (1U << CP0C4_M),
|
||||
.CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB),
|
||||
.CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) |
|
||||
(1 << CP0C5_UFE),
|
||||
.CP0_LLAddr_rw_bitmask = 0,
|
||||
.CP0_LLAddr_shift = 0,
|
||||
.SYNCI_Step = 32,
|
||||
.CCRes = 2,
|
||||
.CP0_Status_rw_bitmask = 0x3158FF1F,
|
||||
.CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
|
||||
(1U << CP0PG_RIE),
|
||||
.CP0_PageGrain_rw_bitmask = 0,
|
||||
.CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
|
||||
(1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
|
||||
(1 << FCR0_S) | (0x02 << FCR0_PRID) | (0x0 << FCR0_REV),
|
||||
.CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
|
||||
.SEGBITS = 32,
|
||||
.PABITS = 32,
|
||||
.insn_flags = CPU_NANOMIPS32 | ASE_DSP | ASE_DSPR2 | ASE_MT,
|
||||
.mmu_type = MMU_TYPE_R4000,
|
||||
},
|
||||
#if defined(TARGET_MIPS64)
|
||||
{
|
||||
.name = "R4000",
|
||||
|
||||
Loading…
Reference in New Issue
Block a user