hw/pxa2xx.c: Convert CLKCFG and PWRMODE cp14 regs
Convert the PXA2xx CLKCFG and PWRMODE cp14 registers to the new arm_cp_reginfo scheme. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
parent
dc2a9045cf
commit
e2f8a44d0d
167
hw/pxa2xx.c
167
hw/pxa2xx.c
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@ -224,131 +224,96 @@ static const VMStateDescription vmstate_pxa2xx_cm = {
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}
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};
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static uint32_t pxa2xx_clkpwr_read(void *opaque, int op2, int reg, int crm)
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static int pxa2xx_clkcfg_read(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t *value)
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{
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PXA2xxState *s = (PXA2xxState *) opaque;
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PXA2xxState *s = (PXA2xxState *)ri->opaque;
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*value = s->clkcfg;
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return 0;
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}
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switch (reg) {
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case 6: /* Clock Configuration register */
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return s->clkcfg;
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case 7: /* Power Mode register */
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return 0;
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default:
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printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
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break;
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static int pxa2xx_clkcfg_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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PXA2xxState *s = (PXA2xxState *)ri->opaque;
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s->clkcfg = value & 0xf;
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if (value & 2) {
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printf("%s: CPU frequency change attempt\n", __func__);
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}
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return 0;
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}
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static void pxa2xx_clkpwr_write(void *opaque, int op2, int reg, int crm,
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uint32_t value)
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static int pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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PXA2xxState *s = (PXA2xxState *) opaque;
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PXA2xxState *s = (PXA2xxState *)ri->opaque;
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static const char *pwrmode[8] = {
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"Normal", "Idle", "Deep-idle", "Standby",
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"Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
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};
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switch (reg) {
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case 6: /* Clock Configuration register */
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s->clkcfg = value & 0xf;
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if (value & 2)
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printf("%s: CPU frequency change attempt\n", __FUNCTION__);
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if (value & 8) {
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printf("%s: CPU voltage change attempt\n", __func__);
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}
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switch (value & 7) {
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case 0:
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/* Do nothing */
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break;
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case 7: /* Power Mode register */
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if (value & 8)
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printf("%s: CPU voltage change attempt\n", __FUNCTION__);
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switch (value & 7) {
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case 0:
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/* Do nothing */
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break;
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case 1:
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/* Idle */
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if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) { /* CPDIS */
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cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HALT);
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break;
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}
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/* Fall through. */
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case 2:
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/* Deep-Idle */
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case 1:
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/* Idle */
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if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) { /* CPDIS */
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cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HALT);
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s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
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goto message;
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break;
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}
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/* Fall through. */
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case 3:
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s->cpu->env.uncached_cpsr =
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ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
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s->cpu->env.cp15.c1_sys = 0;
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s->cpu->env.cp15.c1_coproc = 0;
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s->cpu->env.cp15.c2_base0 = 0;
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s->cpu->env.cp15.c3 = 0;
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s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */
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s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
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case 2:
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/* Deep-Idle */
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cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HALT);
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s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
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goto message;
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/*
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* The scratch-pad register is almost universally used
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* for storing the return address on suspend. For the
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* lack of a resuming bootloader, perform a jump
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* directly to that address.
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*/
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memset(s->cpu->env.regs, 0, 4 * 15);
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s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2];
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case 3:
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s->cpu->env.uncached_cpsr =
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ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
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s->cpu->env.cp15.c1_sys = 0;
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s->cpu->env.cp15.c1_coproc = 0;
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s->cpu->env.cp15.c2_base0 = 0;
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s->cpu->env.cp15.c3 = 0;
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s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */
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s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
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/*
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* The scratch-pad register is almost universally used
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* for storing the return address on suspend. For the
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* lack of a resuming bootloader, perform a jump
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* directly to that address.
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*/
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memset(s->cpu->env.regs, 0, 4 * 15);
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s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2];
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#if 0
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buffer = 0xe59ff000; /* ldr pc, [pc, #0] */
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cpu_physical_memory_write(0, &buffer, 4);
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buffer = s->pm_regs[PSPR >> 2];
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cpu_physical_memory_write(8, &buffer, 4);
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buffer = 0xe59ff000; /* ldr pc, [pc, #0] */
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cpu_physical_memory_write(0, &buffer, 4);
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buffer = s->pm_regs[PSPR >> 2];
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cpu_physical_memory_write(8, &buffer, 4);
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#endif
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/* Suspend */
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cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
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/* Suspend */
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cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
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goto message;
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default:
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message:
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printf("%s: machine entered %s mode\n", __FUNCTION__,
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pwrmode[value & 7]);
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}
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break;
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goto message;
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default:
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printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
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break;
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message:
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printf("%s: machine entered %s mode\n", __func__,
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pwrmode[value & 7]);
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}
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}
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static uint32_t pxa2xx_cp14_read(void *opaque, int op2, int reg, int crm)
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{
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switch (crm) {
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case 0:
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return pxa2xx_clkpwr_read(opaque, op2, reg, crm);
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default:
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printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
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break;
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}
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return 0;
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}
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static void pxa2xx_cp14_write(void *opaque, int op2, int reg, int crm,
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uint32_t value)
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{
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switch (crm) {
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case 0:
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pxa2xx_clkpwr_write(opaque, op2, reg, crm, value);
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break;
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default:
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printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
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break;
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}
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}
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static int pxa2xx_cppmnc_read(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t *value)
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{
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@ -400,6 +365,14 @@ static const ARMCPRegInfo pxa_cp_reginfo[] = {
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "CPPMN3", .cp = 14, .crn = 2, .crm = 3, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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/* cp14 crn==6: CLKCFG */
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{ .name = "CLKCFG", .cp = 14, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW,
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.readfn = pxa2xx_clkcfg_read, .writefn = pxa2xx_clkcfg_write },
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/* cp14 crn==7: PWRMODE */
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{ .name = "PWRMODE", .cp = 14, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW,
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.readfn = arm_cp_read_zero, .writefn = pxa2xx_pwrmode_write },
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REGINFO_SENTINEL
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};
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@ -2111,7 +2084,6 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space,
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memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem);
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vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
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cpu_arm_set_cp_io(&s->cpu->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
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pxa2xx_setup_cp14(s);
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s->mm_base = 0x48000000;
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@ -2243,7 +2215,6 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
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memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem);
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vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
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cpu_arm_set_cp_io(&s->cpu->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
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pxa2xx_setup_cp14(s);
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s->mm_base = 0x48000000;
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