xilinx_zynq: machine model initial version
Xilinx zynq-7000 machine model. Also includes device model for the zynq-specific system level control register (SLCR) module. Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
This commit is contained in:
Peter A. G. Crosthwaite
Edgar E. Iglesias
parent
e9f186e514
commit
e32605062c
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@ -251,6 +251,13 @@ M: Peter Maydell <peter.maydell@linaro.org>
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S: Maintained
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F: hw/versatilepb.c
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Xilinx Zynq
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M: Peter Crosthwaite <peter.crosthwaite@petalogix.com>
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S: Maintained
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F: hw/xilinx_zynq.c
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F: hw/zynq_slcr.c
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F: hw/cadence_*
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CRIS Machines
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-------------
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Axis Dev88
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@ -349,6 +349,7 @@ obj-arm-y += versatile_pci.o
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obj-arm-y += cadence_uart.o
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obj-arm-y += cadence_ttc.o
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obj-arm-y += cadence_gem.o
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obj-arm-y += xilinx_zynq.o zynq_slcr.o
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obj-arm-y += realview_gic.o realview.o arm_sysctl.o arm11mpcore.o a9mpcore.o
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obj-arm-y += exynos4210_gic.o exynos4210_combiner.o exynos4210.o
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obj-arm-y += exynos4_boards.o exynos4210_uart.o exynos4210_pwm.o
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@ -0,0 +1,157 @@
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/*
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* Xilinx Zynq Baseboard System emulation.
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*
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* Copyright (c) 2010 Xilinx.
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* Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.com)
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* Copyright (c) 2012 Petalogix Pty Ltd.
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* Written by Haibing Ma
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "sysbus.h"
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#include "arm-misc.h"
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#include "net.h"
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#include "exec-memory.h"
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#include "sysemu.h"
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#include "boards.h"
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#include "flash.h"
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#include "blockdev.h"
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#include "loader.h"
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#define FLASH_SIZE (64 * 1024 * 1024)
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#define FLASH_SECTOR_SIZE (128 * 1024)
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#define IRQ_OFFSET 32 /* pic interrupts start from index 32 */
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static struct arm_boot_info zynq_binfo = {};
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static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
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{
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DeviceState *dev;
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SysBusDevice *s;
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qemu_check_nic_model(nd, "cadence_gem");
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dev = qdev_create(NULL, "cadence_gem");
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qdev_set_nic_properties(dev, nd);
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qdev_init_nofail(dev);
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s = sysbus_from_qdev(dev);
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sysbus_mmio_map(s, 0, base);
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sysbus_connect_irq(s, 0, irq);
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}
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static void zynq_init(ram_addr_t ram_size, const char *boot_device,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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CPUState *env = NULL;
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MemoryRegion *address_space_mem = get_system_memory();
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MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
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MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
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DeviceState *dev;
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SysBusDevice *busdev;
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qemu_irq *irqp;
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qemu_irq pic[64];
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NICInfo *nd;
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int n;
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qemu_irq cpu_irq;
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if (!cpu_model) {
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cpu_model = "cortex-a9";
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}
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env = cpu_init(cpu_model);
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if (!env) {
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fprintf(stderr, "Unable to find CPU definition\n");
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exit(1);
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}
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irqp = arm_pic_init_cpu(env);
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cpu_irq = irqp[ARM_PIC_CPU_IRQ];
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/* max 2GB ram */
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if (ram_size > 0x80000000) {
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ram_size = 0x80000000;
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}
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/* DDR remapped to address zero. */
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memory_region_init_ram(ext_ram, "zynq.ext_ram", ram_size);
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vmstate_register_ram_global(ext_ram);
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memory_region_add_subregion(address_space_mem, 0, ext_ram);
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/* 256K of on-chip memory */
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memory_region_init_ram(ocm_ram, "zynq.ocm_ram", 256 << 10);
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vmstate_register_ram_global(ocm_ram);
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memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram);
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DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
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/* AMD */
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pflash_cfi02_register(0xe2000000, NULL, "zynq.pflash", FLASH_SIZE,
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dinfo ? dinfo->bdrv : NULL, FLASH_SECTOR_SIZE,
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FLASH_SIZE/FLASH_SECTOR_SIZE, 1,
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1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
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0);
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dev = qdev_create(NULL, "xilinx,zynq_slcr");
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qdev_init_nofail(dev);
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sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0xF8000000);
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dev = qdev_create(NULL, "a9mpcore_priv");
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qdev_prop_set_uint32(dev, "num-cpu", 1);
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qdev_init_nofail(dev);
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busdev = sysbus_from_qdev(dev);
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sysbus_mmio_map(busdev, 0, 0xF8F00000);
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sysbus_connect_irq(busdev, 0, cpu_irq);
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for (n = 0; n < 64; n++) {
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pic[n] = qdev_get_gpio_in(dev, n);
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}
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sysbus_create_simple("cadence_uart", 0xE0000000, pic[59-IRQ_OFFSET]);
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sysbus_create_simple("cadence_uart", 0xE0001000, pic[82-IRQ_OFFSET]);
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sysbus_create_varargs("cadence_ttc", 0xF8001000,
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pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL);
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sysbus_create_varargs("cadence_ttc", 0xF8002000,
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pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL);
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for (n = 0; n < nb_nics; n++) {
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nd = &nd_table[n];
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if (n == 0) {
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gem_init(nd, 0xE000B000, pic[54-IRQ_OFFSET]);
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} else if (n == 1) {
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gem_init(nd, 0xE000C000, pic[77-IRQ_OFFSET]);
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}
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}
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zynq_binfo.ram_size = ram_size;
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zynq_binfo.kernel_filename = kernel_filename;
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zynq_binfo.kernel_cmdline = kernel_cmdline;
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zynq_binfo.initrd_filename = initrd_filename;
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zynq_binfo.nb_cpus = 1;
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zynq_binfo.board_id = 0xd32;
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zynq_binfo.loader_start = 0;
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arm_load_kernel(first_cpu, &zynq_binfo);
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}
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static QEMUMachine zynq_machine = {
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.name = "xilinx-zynq-a9",
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.desc = "Xilinx Zynq Platform Baseboard for Cortex-A9",
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.init = zynq_init,
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.use_scsi = 1,
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.max_cpus = 1,
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.no_sdcard = 1
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};
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static void zynq_machine_init(void)
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{
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qemu_register_machine(&zynq_machine);
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}
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machine_init(zynq_machine_init);
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@ -0,0 +1,535 @@
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/*
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* Status and system control registers for Xilinx Zynq Platform
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*
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* Copyright (c) 2011 Michal Simek <monstr@monstr.eu>
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* Copyright (c) 2012 PetaLogix Pty Ltd.
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* Based on hw/arm_sysctl.c, written by Paul Brook
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hw.h"
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#include "qemu-timer.h"
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#include "sysbus.h"
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#include "sysemu.h"
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#ifdef ZYNQ_ARM_SLCR_ERR_DEBUG
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#define DB_PRINT(...) do { \
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fprintf(stderr, ": %s: ", __func__); \
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fprintf(stderr, ## __VA_ARGS__); \
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} while (0);
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#else
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#define DB_PRINT(...)
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#endif
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#define XILINX_LOCK_KEY 0x767b
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#define XILINX_UNLOCK_KEY 0xdf0d
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typedef enum {
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ARM_PLL_CTRL,
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DDR_PLL_CTRL,
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IO_PLL_CTRL,
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PLL_STATUS,
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ARM_PPL_CFG,
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DDR_PLL_CFG,
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IO_PLL_CFG,
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PLL_BG_CTRL,
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PLL_MAX
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} PLLValues;
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typedef enum {
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ARM_CLK_CTRL,
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DDR_CLK_CTRL,
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DCI_CLK_CTRL,
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APER_CLK_CTRL,
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USB0_CLK_CTRL,
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USB1_CLK_CTRL,
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GEM0_RCLK_CTRL,
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GEM1_RCLK_CTRL,
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GEM0_CLK_CTRL,
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GEM1_CLK_CTRL,
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SMC_CLK_CTRL,
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LQSPI_CLK_CTRL,
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SDIO_CLK_CTRL,
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UART_CLK_CTRL,
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SPI_CLK_CTRL,
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CAN_CLK_CTRL,
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CAN_MIOCLK_CTRL,
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DBG_CLK_CTRL,
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PCAP_CLK_CTRL,
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TOPSW_CLK_CTRL,
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CLK_MAX
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} ClkValues;
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typedef enum {
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CLK_CTRL,
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THR_CTRL,
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THR_CNT,
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THR_STA,
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FPGA_MAX
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} FPGAValues;
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typedef enum {
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SYNC_CTRL,
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SYNC_STATUS,
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BANDGAP_TRIP,
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CC_TEST,
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PLL_PREDIVISOR,
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CLK_621_TRUE,
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PICTURE_DBG,
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PICTURE_DBG_UCNT,
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PICTURE_DBG_LCNT,
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MISC_MAX
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} MiscValues;
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typedef enum {
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PSS,
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DDDR,
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DMAC,
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USB,
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GEM,
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SDIO,
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SPI,
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CAN,
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I2C,
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UART,
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GPIO,
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LQSPI,
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SMC,
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OCM,
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DEVCI,
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FPGA,
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A9_CPU,
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RS_AWDT,
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RST_REASON,
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RST_REASON_CLR,
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REBOOT_STATUS,
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BOOT_MODE,
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RESET_MAX
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} ResetValues;
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typedef struct {
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SysBusDevice busdev;
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MemoryRegion iomem;
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union {
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struct {
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uint16_t scl;
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uint16_t lockval;
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uint32_t pll[PLL_MAX]; /* 0x100 - 0x11C */
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uint32_t clk[CLK_MAX]; /* 0x120 - 0x16C */
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uint32_t fpga[4][FPGA_MAX]; /* 0x170 - 0x1AC */
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uint32_t misc[MISC_MAX]; /* 0x1B0 - 0x1D8 */
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uint32_t reset[RESET_MAX]; /* 0x200 - 0x25C */
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uint32_t apu_ctrl; /* 0x300 */
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uint32_t wdt_clk_sel; /* 0x304 */
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uint32_t tz_ocm[3]; /* 0x400 - 0x408 */
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uint32_t tz_ddr; /* 0x430 */
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uint32_t tz_dma[3]; /* 0x440 - 0x448 */
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uint32_t tz_misc[3]; /* 0x450 - 0x458 */
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uint32_t tz_fpga[2]; /* 0x484 - 0x488 */
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uint32_t dbg_ctrl; /* 0x500 */
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uint32_t pss_idcode; /* 0x530 */
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uint32_t ddr[8]; /* 0x600 - 0x620 - 0x604-missing */
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uint32_t mio[54]; /* 0x700 - 0x7D4 */
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uint32_t mio_func[4]; /* 0x800 - 0x810 */
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uint32_t sd[2]; /* 0x830 - 0x834 */
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uint32_t lvl_shftr_en; /* 0x900 */
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uint32_t ocm_cfg; /* 0x910 */
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uint32_t cpu_ram[8]; /* 0xA00 - 0xA1C */
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uint32_t iou[7]; /* 0xA30 - 0xA48 */
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uint32_t dmac_ram; /* 0xA50 */
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uint32_t afi[4][3]; /* 0xA60 - 0xA8C */
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uint32_t ocm[3]; /* 0xA90 - 0xA98 */
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uint32_t devci_ram; /* 0xAA0 */
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uint32_t csg_ram; /* 0xAB0 */
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uint32_t gpiob[12]; /* 0xB00 - 0xB2C */
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uint32_t ddriob[14]; /* 0xB40 - 0xB74 */
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};
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uint8_t data[0x1000];
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};
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} ZynqSLCRState;
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static void zynq_slcr_reset(DeviceState *d)
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{
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int i;
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ZynqSLCRState *s =
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FROM_SYSBUS(ZynqSLCRState, sysbus_from_qdev(d));
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DB_PRINT("RESET\n");
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s->lockval = 1;
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/* 0x100 - 0x11C */
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s->pll[ARM_PLL_CTRL] = 0x0001A008;
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s->pll[DDR_PLL_CTRL] = 0x0001A008;
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s->pll[IO_PLL_CTRL] = 0x0001A008;
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s->pll[PLL_STATUS] = 0x0000003F;
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s->pll[ARM_PPL_CFG] = 0x00014000;
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s->pll[DDR_PLL_CFG] = 0x00014000;
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s->pll[IO_PLL_CFG] = 0x00014000;
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/* 0x120 - 0x16C */
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s->clk[ARM_CLK_CTRL] = 0x1F000400;
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s->clk[DDR_CLK_CTRL] = 0x18400003;
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s->clk[DCI_CLK_CTRL] = 0x01E03201;
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s->clk[APER_CLK_CTRL] = 0x01FFCCCD;
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s->clk[USB0_CLK_CTRL] = s->clk[USB1_CLK_CTRL] = 0x00101941;
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s->clk[GEM0_RCLK_CTRL] = s->clk[GEM1_RCLK_CTRL] = 0x00000001;
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s->clk[GEM0_CLK_CTRL] = s->clk[GEM1_CLK_CTRL] = 0x00003C01;
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s->clk[SMC_CLK_CTRL] = 0x00003C01;
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s->clk[LQSPI_CLK_CTRL] = 0x00002821;
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s->clk[SDIO_CLK_CTRL] = 0x00001E03;
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s->clk[UART_CLK_CTRL] = 0x00003F03;
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s->clk[SPI_CLK_CTRL] = 0x00003F03;
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s->clk[CAN_CLK_CTRL] = 0x00501903;
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s->clk[DBG_CLK_CTRL] = 0x00000F03;
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s->clk[PCAP_CLK_CTRL] = 0x00000F01;
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/* 0x170 - 0x1AC */
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s->fpga[0][CLK_CTRL] = s->fpga[1][CLK_CTRL] = s->fpga[2][CLK_CTRL] =
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s->fpga[3][CLK_CTRL] = 0x00101800;
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s->fpga[0][THR_STA] = s->fpga[1][THR_STA] = s->fpga[2][THR_STA] =
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s->fpga[3][THR_STA] = 0x00010000;
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/* 0x1B0 - 0x1D8 */
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s->misc[BANDGAP_TRIP] = 0x0000001F;
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s->misc[PLL_PREDIVISOR] = 0x00000001;
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s->misc[CLK_621_TRUE] = 0x00000001;
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/* 0x200 - 0x25C */
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s->reset[FPGA] = 0x01F33F0F;
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s->reset[RST_REASON] = 0x00000040;
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/* 0x700 - 0x7D4 */
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for (i = 0; i < 54; i++) {
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s->mio[i] = 0x00001601;
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}
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for (i = 2; i <= 8; i++) {
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s->mio[i] = 0x00000601;
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}
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/* MIO_MST_TRI0, MIO_MST_TRI1 */
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s->mio_func[2] = s->mio_func[3] = 0xFFFFFFFF;
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s->cpu_ram[0] = s->cpu_ram[1] = s->cpu_ram[3] =
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s->cpu_ram[4] = s->cpu_ram[7] = 0x00010101;
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s->cpu_ram[2] = s->cpu_ram[5] = 0x01010101;
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s->cpu_ram[6] = 0x00000001;
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s->iou[0] = s->iou[1] = s->iou[2] = s->iou[3] = 0x09090909;
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s->iou[4] = s->iou[5] = 0x00090909;
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s->iou[6] = 0x00000909;
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s->dmac_ram = 0x00000009;
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s->afi[0][0] = s->afi[0][1] = 0x09090909;
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s->afi[1][0] = s->afi[1][1] = 0x09090909;
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s->afi[2][0] = s->afi[2][1] = 0x09090909;
|
||||
s->afi[3][0] = s->afi[3][1] = 0x09090909;
|
||||
s->afi[0][2] = s->afi[1][2] = s->afi[2][2] = s->afi[3][2] = 0x00000909;
|
||||
|
||||
s->ocm[0] = 0x01010101;
|
||||
s->ocm[1] = s->ocm[2] = 0x09090909;
|
||||
|
||||
s->devci_ram = 0x00000909;
|
||||
s->csg_ram = 0x00000001;
|
||||
|
||||
s->ddriob[0] = s->ddriob[1] = s->ddriob[2] = s->ddriob[3] = 0x00000e00;
|
||||
s->ddriob[4] = s->ddriob[5] = s->ddriob[6] = 0x00000e00;
|
||||
s->ddriob[12] = 0x00000021;
|
||||
}
|
||||
|
||||
static inline uint32_t zynq_slcr_read_imp(void *opaque,
|
||||
target_phys_addr_t offset)
|
||||
{
|
||||
ZynqSLCRState *s = (ZynqSLCRState *)opaque;
|
||||
|
||||
switch (offset) {
|
||||
case 0x0: /* SCL */
|
||||
return s->scl;
|
||||
case 0x4: /* LOCK */
|
||||
case 0x8: /* UNLOCK */
|
||||
DB_PRINT("Reading SCLR_LOCK/UNLOCK is not enabled\n");
|
||||
return 0;
|
||||
case 0x0C: /* LOCKSTA */
|
||||
return s->lockval;
|
||||
case 0x100 ... 0x11C:
|
||||
return s->pll[(offset - 0x100) / 4];
|
||||
case 0x120 ... 0x16C:
|
||||
return s->clk[(offset - 0x120) / 4];
|
||||
case 0x170 ... 0x1AC:
|
||||
return s->fpga[0][(offset - 0x170) / 4];
|
||||
case 0x1B0 ... 0x1D8:
|
||||
return s->misc[(offset - 0x1B0) / 4];
|
||||
case 0x200 ... 0x258:
|
||||
return s->reset[(offset - 0x200) / 4];
|
||||
case 0x25c:
|
||||
return 1;
|
||||
case 0x300:
|
||||
return s->apu_ctrl;
|
||||
case 0x304:
|
||||
return s->wdt_clk_sel;
|
||||
case 0x400 ... 0x408:
|
||||
return s->tz_ocm[(offset - 0x400) / 4];
|
||||
case 0x430:
|
||||
return s->tz_ddr;
|
||||
case 0x440 ... 0x448:
|
||||
return s->tz_dma[(offset - 0x440) / 4];
|
||||
case 0x450 ... 0x458:
|
||||
return s->tz_misc[(offset - 0x450) / 4];
|
||||
case 0x484 ... 0x488:
|
||||
return s->tz_fpga[(offset - 0x484) / 4];
|
||||
case 0x500:
|
||||
return s->dbg_ctrl;
|
||||
case 0x530:
|
||||
return s->pss_idcode;
|
||||
case 0x600 ... 0x620:
|
||||
if (offset == 0x604) {
|
||||
goto bad_reg;
|
||||
}
|
||||
return s->ddr[(offset - 0x600) / 4];
|
||||
case 0x700 ... 0x7D4:
|
||||
return s->mio[(offset - 0x700) / 4];
|
||||
case 0x800 ... 0x810:
|
||||
return s->mio_func[(offset - 0x800) / 4];
|
||||
case 0x830 ... 0x834:
|
||||
return s->sd[(offset - 0x830) / 4];
|
||||
case 0x900:
|
||||
return s->lvl_shftr_en;
|
||||
case 0x910:
|
||||
return s->ocm_cfg;
|
||||
case 0xA00 ... 0xA1C:
|
||||
return s->cpu_ram[(offset - 0xA00) / 4];
|
||||
case 0xA30 ... 0xA48:
|
||||
return s->iou[(offset - 0xA30) / 4];
|
||||
case 0xA50:
|
||||
return s->dmac_ram;
|
||||
case 0xA60 ... 0xA8C:
|
||||
return s->afi[0][(offset - 0x700) / 4];
|
||||
case 0xA90 ... 0xA98:
|
||||
return s->ocm[(offset - 0xA90) / 4];
|
||||
case 0xAA0:
|
||||
return s->devci_ram;
|
||||
case 0xAB0:
|
||||
return s->csg_ram;
|
||||
case 0xB00 ... 0xB2C:
|
||||
return s->gpiob[(offset - 0xB00) / 4];
|
||||
case 0xB40 ... 0xB74:
|
||||
return s->ddriob[(offset - 0xB40) / 4];
|
||||
default:
|
||||
bad_reg:
|
||||
DB_PRINT("Bad register offset 0x%x\n", (int)offset);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
static uint64_t zynq_slcr_read(void *opaque, target_phys_addr_t offset,
|
||||
unsigned size)
|
||||
{
|
||||
uint32_t ret = zynq_slcr_read_imp(opaque, offset);
|
||||
|
||||
DB_PRINT("addr: %08x data: %08x\n", offset, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void zynq_slcr_write(void *opaque, target_phys_addr_t offset,
|
||||
uint64_t val, unsigned size)
|
||||
{
|
||||
ZynqSLCRState *s = (ZynqSLCRState *)opaque;
|
||||
|
||||
DB_PRINT("offset: %08x data: %08x\n", offset, (unsigned)val);
|
||||
|
||||
switch (offset) {
|
||||
case 0x00: /* SCL */
|
||||
s->scl = val & 0x1;
|
||||
return;
|
||||
case 0x4: /* SLCR_LOCK */
|
||||
if ((val & 0xFFFF) == XILINX_LOCK_KEY) {
|
||||
DB_PRINT("XILINX LOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset,
|
||||
(unsigned)val & 0xFFFF);
|
||||
s->lockval = 1;
|
||||
} else {
|
||||
DB_PRINT("WRONG XILINX LOCK KEY 0xF8000000 + 0x%x <= 0x%x\n",
|
||||
(int)offset, (unsigned)val & 0xFFFF);
|
||||
}
|
||||
return;
|
||||
case 0x8: /* SLCR_UNLOCK */
|
||||
if ((val & 0xFFFF) == XILINX_UNLOCK_KEY) {
|
||||
DB_PRINT("XILINX UNLOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset,
|
||||
(unsigned)val & 0xFFFF);
|
||||
s->lockval = 0;
|
||||
} else {
|
||||
DB_PRINT("WRONG XILINX UNLOCK KEY 0xF8000000 + 0x%x <= 0x%x\n",
|
||||
(int)offset, (unsigned)val & 0xFFFF);
|
||||
}
|
||||
return;
|
||||
case 0xc: /* LOCKSTA */
|
||||
DB_PRINT("Writing SCLR_LOCKSTA is not enabled\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if (!s->lockval) {
|
||||
switch (offset) {
|
||||
case 0x100 ... 0x11C:
|
||||
if (offset == 0x10C) {
|
||||
goto bad_reg;
|
||||
}
|
||||
s->pll[(offset - 0x100) / 4] = val;
|
||||
break;
|
||||
case 0x120 ... 0x16C:
|
||||
s->clk[(offset - 0x120) / 4] = val;
|
||||
break;
|
||||
case 0x170 ... 0x1AC:
|
||||
s->fpga[0][(offset - 0x170) / 4] = val;
|
||||
break;
|
||||
case 0x1B0 ... 0x1D8:
|
||||
s->misc[(offset - 0x1B0) / 4] = val;
|
||||
break;
|
||||
case 0x200 ... 0x25C:
|
||||
if (offset == 0x250) {
|
||||
goto bad_reg;
|
||||
}
|
||||
s->reset[(offset - 0x200) / 4] = val;
|
||||
break;
|
||||
case 0x300:
|
||||
s->apu_ctrl = val;
|
||||
break;
|
||||
case 0x304:
|
||||
s->wdt_clk_sel = val;
|
||||
break;
|
||||
case 0x400 ... 0x408:
|
||||
s->tz_ocm[(offset - 0x400) / 4] = val;
|
||||
break;
|
||||
case 0x430:
|
||||
s->tz_ddr = val;
|
||||
break;
|
||||
case 0x440 ... 0x448:
|
||||
s->tz_dma[(offset - 0x440) / 4] = val;
|
||||
break;
|
||||
case 0x450 ... 0x458:
|
||||
s->tz_misc[(offset - 0x450) / 4] = val;
|
||||
break;
|
||||
case 0x484 ... 0x488:
|
||||
s->tz_fpga[(offset - 0x484) / 4] = val;
|
||||
break;
|
||||
case 0x500:
|
||||
s->dbg_ctrl = val;
|
||||
break;
|
||||
case 0x530:
|
||||
s->pss_idcode = val;
|
||||
break;
|
||||
case 0x600 ... 0x620:
|
||||
if (offset == 0x604) {
|
||||
goto bad_reg;
|
||||
}
|
||||
s->ddr[(offset - 0x600) / 4] = val;
|
||||
break;
|
||||
case 0x700 ... 0x7D4:
|
||||
s->mio[(offset - 0x700) / 4] = val;
|
||||
break;
|
||||
case 0x800 ... 0x810:
|
||||
s->mio_func[(offset - 0x800) / 4] = val;
|
||||
break;
|
||||
case 0x830 ... 0x834:
|
||||
s->sd[(offset - 0x830) / 4] = val;
|
||||
break;
|
||||
case 0x900:
|
||||
s->lvl_shftr_en = val;
|
||||
break;
|
||||
case 0x910:
|
||||
break;
|
||||
case 0xA00 ... 0xA1C:
|
||||
s->cpu_ram[(offset - 0xA00) / 4] = val;
|
||||
break;
|
||||
case 0xA30 ... 0xA48:
|
||||
s->iou[(offset - 0xA30) / 4] = val;
|
||||
break;
|
||||
case 0xA50:
|
||||
s->dmac_ram = val;
|
||||
break;
|
||||
case 0xA60 ... 0xA8C:
|
||||
s->afi[0][(offset - 0x700) / 4] = val;
|
||||
break;
|
||||
case 0xA90:
|
||||
s->ocm[0] = val;
|
||||
break;
|
||||
case 0xAA0:
|
||||
s->devci_ram = val;
|
||||
break;
|
||||
case 0xAB0:
|
||||
s->csg_ram = val;
|
||||
break;
|
||||
case 0xB00 ... 0xB2C:
|
||||
if (offset == 0xB20 || offset == 0xB2C) {
|
||||
goto bad_reg;
|
||||
}
|
||||
s->gpiob[(offset - 0xB00) / 4] = val;
|
||||
break;
|
||||
case 0xB40 ... 0xB74:
|
||||
s->ddriob[(offset - 0xB40) / 4] = val;
|
||||
break;
|
||||
default:
|
||||
bad_reg:
|
||||
DB_PRINT("Bad register write %x <= %08x\n", (int)offset, val);
|
||||
}
|
||||
} else {
|
||||
DB_PRINT("SCLR registers are locked. Unlock them first\n");
|
||||
}
|
||||
}
|
||||
|
||||
static const MemoryRegionOps slcr_ops = {
|
||||
.read = zynq_slcr_read,
|
||||
.write = zynq_slcr_write,
|
||||
.endianness = DEVICE_NATIVE_ENDIAN,
|
||||
};
|
||||
|
||||
static int zynq_slcr_init(SysBusDevice *dev)
|
||||
{
|
||||
ZynqSLCRState *s = FROM_SYSBUS(ZynqSLCRState, dev);
|
||||
|
||||
memory_region_init_io(&s->iomem, &slcr_ops, s, "slcr", 0x1000);
|
||||
sysbus_init_mmio(dev, &s->iomem);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const VMStateDescription vmstate_zynq_slcr = {
|
||||
.name = "zynq_slcr",
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.minimum_version_id_old = 1,
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_UINT8_ARRAY(data, ZynqSLCRState, 0x1000),
|
||||
VMSTATE_END_OF_LIST()
|
||||
}
|
||||
};
|
||||
|
||||
static void zynq_slcr_class_init(ObjectClass *klass, void *data)
|
||||
{
|
||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||
SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
|
||||
|
||||
sdc->init = zynq_slcr_init;
|
||||
dc->vmsd = &vmstate_zynq_slcr;
|
||||
dc->reset = zynq_slcr_reset;
|
||||
}
|
||||
|
||||
static TypeInfo zynq_slcr_info = {
|
||||
.class_init = zynq_slcr_class_init,
|
||||
.name = "xilinx,zynq_slcr",
|
||||
.parent = TYPE_SYS_BUS_DEVICE,
|
||||
.instance_size = sizeof(ZynqSLCRState),
|
||||
};
|
||||
|
||||
static void zynq_slcr_register_types(void)
|
||||
{
|
||||
type_register_static(&zynq_slcr_info);
|
||||
}
|
||||
|
||||
type_init(zynq_slcr_register_types)
|
||||
Loading…
Reference in New Issue