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Factor out common SharpSL PDA code (Dmitry Baryshkov). 

Factor out to sharpsl code to support devices that are present not only
in spitz-family PDAs but also in outher Sharp Zaurus PDAs

Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4642 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
balrog 2008-06-02 01:20:15 +00:00
parent 5c49b363dc
commit e33d8cdb55
4 changed files with 324 additions and 288 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Makefile.target
View File

@ -585,7 +585,7 @@ OBJS+= arm-semi.o
OBJS+= pxa2xx.o pxa2xx_pic.o pxa2xx_gpio.o pxa2xx_timer.o pxa2xx_dma.o
OBJS+= pxa2xx_lcd.o pxa2xx_mmci.o pxa2xx_pcmcia.o pxa2xx_keypad.o
OBJS+= pflash_cfi01.o gumstix.o
OBJS+= spitz.o ide.o serial.o nand.o ecc.o
OBJS+= spitz.o zaurus.o ide.o serial.o nand.o ecc.o
OBJS+= omap1.o omap_lcdc.o omap_dma.o omap_clk.o omap_mmc.o omap_i2c.o
OBJS+= omap2.o omap_dss.o
OBJS+= palm.o tsc210x.o

15
hw/sharpsl.h Normal file
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@ -0,0 +1,15 @@
#ifndef QEMU_SHARPSL_H
#define QEMU_SHARPSL_H
/* zaurus.c */
struct scoop_info_s *scoop_init(struct pxa2xx_state_s *cpu,
int instance, target_phys_addr_t target_base);
void scoop_gpio_set(void *opaque, int line, int level);
qemu_irq *scoop_gpio_in_get(struct scoop_info_s *s);
void scoop_gpio_out_set(struct scoop_info_s *s, int line,
qemu_irq handler);
#define SL_PXA_PARAM_BASE 0xa0000a00
void sl_bootparam_write(uint32_t ptr);
#endif

303
hw/spitz.c
View File

@ -16,6 +16,7 @@
#include "flash.h"
#include "qemu-timer.h"
#include "devices.h"
#include "sharpsl.h"
#include "console.h"
#include "block.h"
#include "audio/audio.h"
@ -520,238 +521,6 @@ static void spitz_keyboard_register(struct pxa2xx_state_s *cpu)
spitz_keyboard_save, spitz_keyboard_load, s);
}
/* SCOOP devices */
struct scoop_info_s {
target_phys_addr_t target_base;
qemu_irq handler[16];
qemu_irq *in;
uint16_t status;
uint16_t power;
uint32_t gpio_level;
uint32_t gpio_dir;
uint32_t prev_level;
uint16_t mcr;
uint16_t cdr;
uint16_t ccr;
uint16_t irr;
uint16_t imr;
uint16_t isr;
uint16_t gprr;
};
#define SCOOP_MCR 0x00
#define SCOOP_CDR 0x04
#define SCOOP_CSR 0x08
#define SCOOP_CPR 0x0c
#define SCOOP_CCR 0x10
#define SCOOP_IRR_IRM 0x14
#define SCOOP_IMR 0x18
#define SCOOP_ISR 0x1c
#define SCOOP_GPCR 0x20
#define SCOOP_GPWR 0x24
#define SCOOP_GPRR 0x28
static inline void scoop_gpio_handler_update(struct scoop_info_s *s) {
uint32_t level, diff;
int bit;
level = s->gpio_level & s->gpio_dir;
for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
bit = ffs(diff) - 1;
qemu_set_irq(s->handler[bit], (level >> bit) & 1);
}
s->prev_level = level;
}
static uint32_t scoop_readb(void *opaque, target_phys_addr_t addr)
{
struct scoop_info_s *s = (struct scoop_info_s *) opaque;
addr -= s->target_base;
switch (addr) {
case SCOOP_MCR:
return s->mcr;
case SCOOP_CDR:
return s->cdr;
case SCOOP_CSR:
return s->status;
case SCOOP_CPR:
return s->power;
case SCOOP_CCR:
return s->ccr;
case SCOOP_IRR_IRM:
return s->irr;
case SCOOP_IMR:
return s->imr;
case SCOOP_ISR:
return s->isr;
case SCOOP_GPCR:
return s->gpio_dir;
case SCOOP_GPWR:
return s->gpio_level;
case SCOOP_GPRR:
return s->gprr;
default:
spitz_printf("Bad register offset " REG_FMT "\n", addr);
}
return 0;
}
static void scoop_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
{
struct scoop_info_s *s = (struct scoop_info_s *) opaque;
addr -= s->target_base;
value &= 0xffff;
switch (addr) {
case SCOOP_MCR:
s->mcr = value;
break;
case SCOOP_CDR:
s->cdr = value;
break;
case SCOOP_CPR:
s->power = value;
if (value & 0x80)
s->power |= 0x8040;
break;
case SCOOP_CCR:
s->ccr = value;
break;
case SCOOP_IRR_IRM:
s->irr = value;
break;
case SCOOP_IMR:
s->imr = value;
break;
case SCOOP_ISR:
s->isr = value;
break;
case SCOOP_GPCR:
s->gpio_dir = value;
scoop_gpio_handler_update(s);
break;
case SCOOP_GPWR:
s->gpio_level = value & s->gpio_dir;
scoop_gpio_handler_update(s);
break;
case SCOOP_GPRR:
s->gprr = value;
break;
default:
spitz_printf("Bad register offset " REG_FMT "\n", addr);
}
}
CPUReadMemoryFunc *scoop_readfn[] = {
scoop_readb,
scoop_readb,
scoop_readb,
};
CPUWriteMemoryFunc *scoop_writefn[] = {
scoop_writeb,
scoop_writeb,
scoop_writeb,
};
static void scoop_gpio_set(void *opaque, int line, int level)
{
struct scoop_info_s *s = (struct scoop_info_s *) s;
if (level)
s->gpio_level |= (1 << line);
else
s->gpio_level &= ~(1 << line);
}
static inline qemu_irq *scoop_gpio_in_get(struct scoop_info_s *s)
{
return s->in;
}
static inline void scoop_gpio_out_set(struct scoop_info_s *s, int line,
qemu_irq handler) {
if (line >= 16) {
spitz_printf("No GPIO pin %i\n", line);
return;
}
s->handler[line] = handler;
}
static void scoop_save(QEMUFile *f, void *opaque)
{
struct scoop_info_s *s = (struct scoop_info_s *) opaque;
qemu_put_be16s(f, &s->status);
qemu_put_be16s(f, &s->power);
qemu_put_be32s(f, &s->gpio_level);
qemu_put_be32s(f, &s->gpio_dir);
qemu_put_be32s(f, &s->prev_level);
qemu_put_be16s(f, &s->mcr);
qemu_put_be16s(f, &s->cdr);
qemu_put_be16s(f, &s->ccr);
qemu_put_be16s(f, &s->irr);
qemu_put_be16s(f, &s->imr);
qemu_put_be16s(f, &s->isr);
qemu_put_be16s(f, &s->gprr);
}
static int scoop_load(QEMUFile *f, void *opaque, int version_id)
{
struct scoop_info_s *s = (struct scoop_info_s *) opaque;
qemu_get_be16s(f, &s->status);
qemu_get_be16s(f, &s->power);
qemu_get_be32s(f, &s->gpio_level);
qemu_get_be32s(f, &s->gpio_dir);
qemu_get_be32s(f, &s->prev_level);
qemu_get_be16s(f, &s->mcr);
qemu_get_be16s(f, &s->cdr);
qemu_get_be16s(f, &s->ccr);
qemu_get_be16s(f, &s->irr);
qemu_get_be16s(f, &s->imr);
qemu_get_be16s(f, &s->isr);
qemu_get_be16s(f, &s->gprr);
return 0;
}
static struct scoop_info_s *spitz_scoop_init(struct pxa2xx_state_s *cpu,
int count) {
int iomemtype;
struct scoop_info_s *s;
s = (struct scoop_info_s *)
qemu_mallocz(sizeof(struct scoop_info_s) * 2);
memset(s, 0, sizeof(struct scoop_info_s) * count);
s[0].target_base = 0x10800000;
s[1].target_base = 0x08800040;
/* Ready */
s[0].status = 0x02;
s[1].status = 0x02;
s[0].in = qemu_allocate_irqs(scoop_gpio_set, &s[0], 16);
iomemtype = cpu_register_io_memory(0, scoop_readfn,
scoop_writefn, &s[0]);
cpu_register_physical_memory(s[0].target_base, 0x1000, iomemtype);
register_savevm("scoop", 0, 0, scoop_save, scoop_load, &s[0]);
if (count < 2)
return s;
s[1].in = qemu_allocate_irqs(scoop_gpio_set, &s[1], 16);
iomemtype = cpu_register_io_memory(0, scoop_readfn,
scoop_writefn, &s[1]);
cpu_register_physical_memory(s[1].target_base, 0x1000, iomemtype);
register_savevm("scoop", 1, 0, scoop_save, scoop_load, &s[1]);
return s;
}
/* LCD backlight controller */
#define LCDTG_RESCTL 0x00
@ -1050,21 +819,21 @@ static void spitz_out_switch(void *opaque, int line, int level)
#define SPITZ_SCP2_MIC_BIAS 9
static void spitz_scoop_gpio_setup(struct pxa2xx_state_s *cpu,
struct scoop_info_s *scp, int num)
struct scoop_info_s *scp0, struct scoop_info_s *scp1)
{
qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, cpu, 8);
scoop_gpio_out_set(&scp[0], SPITZ_SCP_CHRG_ON, outsignals[0]);
scoop_gpio_out_set(&scp[0], SPITZ_SCP_JK_B, outsignals[1]);
scoop_gpio_out_set(&scp[0], SPITZ_SCP_LED_GREEN, outsignals[2]);
scoop_gpio_out_set(&scp[0], SPITZ_SCP_LED_ORANGE, outsignals[3]);
scoop_gpio_out_set(scp0, SPITZ_SCP_CHRG_ON, outsignals[0]);
scoop_gpio_out_set(scp0, SPITZ_SCP_JK_B, outsignals[1]);
scoop_gpio_out_set(scp0, SPITZ_SCP_LED_GREEN, outsignals[2]);
scoop_gpio_out_set(scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]);
if (num >= 2) {
scoop_gpio_out_set(&scp[1], SPITZ_SCP2_BACKLIGHT_CONT, outsignals[4]);
scoop_gpio_out_set(&scp[1], SPITZ_SCP2_BACKLIGHT_ON, outsignals[5]);
if (scp1) {
scoop_gpio_out_set(scp1, SPITZ_SCP2_BACKLIGHT_CONT, outsignals[4]);
scoop_gpio_out_set(scp1, SPITZ_SCP2_BACKLIGHT_ON, outsignals[5]);
}
scoop_gpio_out_set(&scp[0], SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
scoop_gpio_out_set(scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
}
#define SPITZ_GPIO_HSYNC 22
@ -1134,49 +903,6 @@ static void spitz_gpio_setup(struct pxa2xx_state_s *cpu, int slots)
spitz_gpio_invert[4]);
}
/* Write the bootloader parameters memory area. */
#define MAGIC_CHG(a, b, c, d) ((d << 24) | (c << 16) | (b << 8) | a)
struct __attribute__ ((__packed__)) sl_param_info {
uint32_t comadj_keyword;
int32_t comadj;
uint32_t uuid_keyword;
char uuid[16];
uint32_t touch_keyword;
int32_t touch_xp;
int32_t touch_yp;
int32_t touch_xd;
int32_t touch_yd;
uint32_t adadj_keyword;
int32_t adadj;
uint32_t phad_keyword;
int32_t phadadj;
} spitz_bootparam = {
.comadj_keyword = MAGIC_CHG('C', 'M', 'A', 'D'),
.comadj = 125,
.uuid_keyword = MAGIC_CHG('U', 'U', 'I', 'D'),
.uuid = { -1 },
.touch_keyword = MAGIC_CHG('T', 'U', 'C', 'H'),
.touch_xp = -1,
.adadj_keyword = MAGIC_CHG('B', 'V', 'A', 'D'),
.adadj = -1,
.phad_keyword = MAGIC_CHG('P', 'H', 'A', 'D'),
.phadadj = 0x01,
};
static void sl_bootparam_write(uint32_t ptr)
{
memcpy(phys_ram_base + ptr, &spitz_bootparam,
sizeof(struct sl_param_info));
}
#define SL_PXA_PARAM_BASE 0xa0000a00
/* Board init. */
enum spitz_model_e { spitz, akita, borzoi, terrier };
@ -1194,7 +920,7 @@ static void spitz_common_init(ram_addr_t ram_size, int vga_ram_size,
const char *cpu_model, enum spitz_model_e model, int arm_id)
{
struct pxa2xx_state_s *cpu;
struct scoop_info_s *scp;
struct scoop_info_s *scp0, *scp1 = NULL;
if (!cpu_model)
cpu_model = (model == terrier) ? "pxa270-c5" : "pxa270-c0";
@ -1217,9 +943,12 @@ static void spitz_common_init(ram_addr_t ram_size, int vga_ram_size,
spitz_ssp_attach(cpu);
scp = spitz_scoop_init(cpu, (model == akita) ? 1 : 2);
scp0 = scoop_init(cpu, 0, 0x10800000);
if (model != akita) {
scp1 = scoop_init(cpu, 1, 0x08800040);
}
spitz_scoop_gpio_setup(cpu, scp, (model == akita) ? 1 : 2);
spitz_scoop_gpio_setup(cpu, scp0, scp1);
spitz_gpio_setup(cpu, (model == akita) ? 1 : 2);

292
hw/zaurus.c Normal file
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@ -0,0 +1,292 @@
/*
* Copyright (c) 2006-2008 Openedhand Ltd.
* Written by Andrzej Zaborowski <balrog@zabor.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 or
* (at your option) version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include "hw.h"
#include "pxa.h"
#include "sharpsl.h"
#define zaurus_printf(format, ...) \
fprintf(stderr, "%s: " format, __FUNCTION__, ##__VA_ARGS__)
#undef REG_FMT
#if TARGET_PHYS_ADDR_BITS == 32
#define REG_FMT "0x%02x"
#else
#define REG_FMT "0x%02lx"
#endif
/* SCOOP devices */
struct scoop_info_s {
target_phys_addr_t target_base;
qemu_irq handler[16];
qemu_irq *in;
uint16_t status;
uint16_t power;
uint32_t gpio_level;
uint32_t gpio_dir;
uint32_t prev_level;
uint16_t mcr;
uint16_t cdr;
uint16_t ccr;
uint16_t irr;
uint16_t imr;
uint16_t isr;
uint16_t gprr;
};
#define SCOOP_MCR 0x00
#define SCOOP_CDR 0x04
#define SCOOP_CSR 0x08
#define SCOOP_CPR 0x0c
#define SCOOP_CCR 0x10
#define SCOOP_IRR_IRM 0x14
#define SCOOP_IMR 0x18
#define SCOOP_ISR 0x1c
#define SCOOP_GPCR 0x20
#define SCOOP_GPWR 0x24
#define SCOOP_GPRR 0x28
static inline void scoop_gpio_handler_update(struct scoop_info_s *s) {
uint32_t level, diff;
int bit;
level = s->gpio_level & s->gpio_dir;
for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
bit = ffs(diff) - 1;
qemu_set_irq(s->handler[bit], (level >> bit) & 1);
}
s->prev_level = level;
}
static uint32_t scoop_readb(void *opaque, target_phys_addr_t addr)
{
struct scoop_info_s *s = (struct scoop_info_s *) opaque;
addr -= s->target_base;
switch (addr) {
case SCOOP_MCR:
return s->mcr;
case SCOOP_CDR:
return s->cdr;
case SCOOP_CSR:
return s->status;
case SCOOP_CPR:
return s->power;
case SCOOP_CCR:
return s->ccr;
case SCOOP_IRR_IRM:
return s->irr;
case SCOOP_IMR:
return s->imr;
case SCOOP_ISR:
return s->isr;
case SCOOP_GPCR:
return s->gpio_dir;
case SCOOP_GPWR:
return s->gpio_level;
case SCOOP_GPRR:
return s->gprr;
default:
zaurus_printf("Bad register offset " REG_FMT "\n", addr);
}
return 0;
}
static void scoop_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
{
struct scoop_info_s *s = (struct scoop_info_s *) opaque;
addr -= s->target_base;
value &= 0xffff;
switch (addr) {
case SCOOP_MCR:
s->mcr = value;
break;
case SCOOP_CDR:
s->cdr = value;
break;
case SCOOP_CPR:
s->power = value;
if (value & 0x80)
s->power |= 0x8040;
break;
case SCOOP_CCR:
s->ccr = value;
break;
case SCOOP_IRR_IRM:
s->irr = value;
break;
case SCOOP_IMR:
s->imr = value;
break;
case SCOOP_ISR:
s->isr = value;
break;
case SCOOP_GPCR:
s->gpio_dir = value;
scoop_gpio_handler_update(s);
break;
case SCOOP_GPWR:
s->gpio_level = value & s->gpio_dir;
scoop_gpio_handler_update(s);
break;
case SCOOP_GPRR:
s->gprr = value;
break;
default:
zaurus_printf("Bad register offset " REG_FMT "\n", addr);
}
}
CPUReadMemoryFunc *scoop_readfn[] = {
scoop_readb,
scoop_readb,
scoop_readb,
};
CPUWriteMemoryFunc *scoop_writefn[] = {
scoop_writeb,
scoop_writeb,
scoop_writeb,
};
void scoop_gpio_set(void *opaque, int line, int level)
{
struct scoop_info_s *s = (struct scoop_info_s *) s;
if (level)
s->gpio_level |= (1 << line);
else
s->gpio_level &= ~(1 << line);
}
qemu_irq *scoop_gpio_in_get(struct scoop_info_s *s)
{
return s->in;
}
void scoop_gpio_out_set(struct scoop_info_s *s, int line,
qemu_irq handler) {
if (line >= 16) {
fprintf(stderr, "No GPIO pin %i\n", line);
exit(-1);
}
s->handler[line] = handler;
}
static void scoop_save(QEMUFile *f, void *opaque)
{
struct scoop_info_s *s = (struct scoop_info_s *) opaque;
qemu_put_be16s(f, &s->status);
qemu_put_be16s(f, &s->power);
qemu_put_be32s(f, &s->gpio_level);
qemu_put_be32s(f, &s->gpio_dir);
qemu_put_be32s(f, &s->prev_level);
qemu_put_be16s(f, &s->mcr);
qemu_put_be16s(f, &s->cdr);
qemu_put_be16s(f, &s->ccr);
qemu_put_be16s(f, &s->irr);
qemu_put_be16s(f, &s->imr);
qemu_put_be16s(f, &s->isr);
qemu_put_be16s(f, &s->gprr);
}
static int scoop_load(QEMUFile *f, void *opaque, int version_id)
{
struct scoop_info_s *s = (struct scoop_info_s *) opaque;
qemu_get_be16s(f, &s->status);
qemu_get_be16s(f, &s->power);
qemu_get_be32s(f, &s->gpio_level);
qemu_get_be32s(f, &s->gpio_dir);
qemu_get_be32s(f, &s->prev_level);
qemu_get_be16s(f, &s->mcr);
qemu_get_be16s(f, &s->cdr);
qemu_get_be16s(f, &s->ccr);
qemu_get_be16s(f, &s->irr);
qemu_get_be16s(f, &s->imr);
qemu_get_be16s(f, &s->isr);
qemu_get_be16s(f, &s->gprr);
return 0;
}
struct scoop_info_s *scoop_init(struct pxa2xx_state_s *cpu,
int instance,
target_phys_addr_t target_base) {
int iomemtype;
struct scoop_info_s *s;
s = (struct scoop_info_s *)
qemu_mallocz(sizeof(struct scoop_info_s));
memset(s, 0, sizeof(struct scoop_info_s));
s->target_base = target_base;
s->status = 0x02;
s->in = qemu_allocate_irqs(scoop_gpio_set, s, 16);
iomemtype = cpu_register_io_memory(0, scoop_readfn,
scoop_writefn, s);
cpu_register_physical_memory(s->target_base, 0x1000, iomemtype);
register_savevm("scoop", instance, 0, scoop_save, scoop_load, s);
return s;
}
/* Write the bootloader parameters memory area. */
#define MAGIC_CHG(a, b, c, d) ((d << 24) | (c << 16) | (b << 8) | a)
struct __attribute__ ((__packed__)) sl_param_info {
uint32_t comadj_keyword;
int32_t comadj;
uint32_t uuid_keyword;
char uuid[16];
uint32_t touch_keyword;
int32_t touch_xp;
int32_t touch_yp;
int32_t touch_xd;
int32_t touch_yd;
uint32_t adadj_keyword;
int32_t adadj;
uint32_t phad_keyword;
int32_t phadadj;
} zaurus_bootparam = {
.comadj_keyword = MAGIC_CHG('C', 'M', 'A', 'D'),
.comadj = 125,
.uuid_keyword = MAGIC_CHG('U', 'U', 'I', 'D'),
.uuid = { -1 },
.touch_keyword = MAGIC_CHG('T', 'U', 'C', 'H'),
.touch_xp = -1,
.adadj_keyword = MAGIC_CHG('B', 'V', 'A', 'D'),
.adadj = -1,
.phad_keyword = MAGIC_CHG('P', 'H', 'A', 'D'),
.phadadj = 0x01,
};
void sl_bootparam_write(uint32_t ptr)
{
memcpy(phys_ram_base + ptr, &zaurus_bootparam,
sizeof(struct sl_param_info));
}