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Generate better code for Sparc32 shifts

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4467 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1 2008-05-17 09:43:12 +00:00
parent 9a7f32283c
commit e35298cd1f
1 changed files with 21 additions and 6 deletions
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27
target-sparc/translate.c
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@ -3008,18 +3008,33 @@ static void disas_sparc_insn(DisasContext * dc)
break;
#ifndef TARGET_SPARC64
case 0x25: /* sll */
tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
if (IS_IMM) { /* immediate */
rs2 = GET_FIELDs(insn, 20, 31);
tcg_gen_shli_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
} else { /* register */
tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
}
gen_movl_TN_reg(rd, cpu_dst);
break;
case 0x26: /* srl */
tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
if (IS_IMM) { /* immediate */
rs2 = GET_FIELDs(insn, 20, 31);
tcg_gen_shri_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
} else { /* register */
tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
}
gen_movl_TN_reg(rd, cpu_dst);
break;
case 0x27: /* sra */
tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
if (IS_IMM) { /* immediate */
rs2 = GET_FIELDs(insn, 20, 31);
tcg_gen_sari_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
} else { /* register */
tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
}
gen_movl_TN_reg(rd, cpu_dst);
break;
#endif