hw:piix4:acpi: reuse pcihp code for legacy PCI hotplug
reduces acpi PCI hotplug code duplication by ~200LOC Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Igor Mammedov
Michael S. Tsirkin
parent
a1b4d9eff9
commit
e358edc8e9
@ -46,8 +46,9 @@
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# define ACPI_PCIHP_DPRINTF(format, ...) do { } while (0)
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#endif
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#define PCI_HOTPLUG_ADDR 0xae00
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#define PCI_HOTPLUG_SIZE 0x0014
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#define ACPI_PCIHP_ADDR 0xae00
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#define ACPI_PCIHP_SIZE 0x0014
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#define ACPI_PCIHP_LEGACY_SIZE 0x000f
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#define PCI_UP_BASE 0x0000
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#define PCI_DOWN_BASE 0x0004
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#define PCI_EJ_BASE 0x0008
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@ -277,12 +278,24 @@ static const MemoryRegionOps acpi_pcihp_io_ops = {
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void acpi_pcihp_init(AcpiPciHpState *s, PCIBus *root_bus,
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MemoryRegion *address_space_io, bool bridges_enabled)
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{
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uint16_t io_size = ACPI_PCIHP_SIZE;
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s->root= root_bus;
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s->legacy_piix = !bridges_enabled;
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if (s->legacy_piix) {
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unsigned *bus_bsel = g_malloc(sizeof *bus_bsel);
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io_size = ACPI_PCIHP_LEGACY_SIZE;
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*bus_bsel = ACPI_PCIHP_BSEL_DEFAULT;
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object_property_add_uint32_ptr(OBJECT(root_bus), ACPI_PCIHP_PROP_BSEL,
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bus_bsel, NULL);
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}
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memory_region_init_io(&s->io, NULL, &acpi_pcihp_io_ops, s,
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"acpi-pci-hotplug",
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PCI_HOTPLUG_SIZE);
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memory_region_add_subregion(address_space_io, PCI_HOTPLUG_ADDR, &s->io);
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"acpi-pci-hotplug", io_size);
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memory_region_add_subregion(address_space_io, ACPI_PCIHP_ADDR, &s->io);
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}
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const VMStateDescription vmstate_acpi_pcihp_pci_status = {
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211
hw/acpi/piix4.c
211
hw/acpi/piix4.c
@ -44,13 +44,6 @@
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#define GPE_BASE 0xafe0
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#define GPE_LEN 4
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#define PCI_HOTPLUG_ADDR 0xae00
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#define PCI_HOTPLUG_SIZE 0x000f
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#define PCI_UP_BASE 0xae00
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#define PCI_DOWN_BASE 0xae04
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#define PCI_EJ_BASE 0xae08
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#define PCI_RMV_BASE 0xae0c
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#define PIIX4_PCI_HOTPLUG_STATUS 2
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struct pci_status {
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@ -80,13 +73,6 @@ typedef struct PIIX4PMState {
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Notifier machine_ready;
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Notifier powerdown_notifier;
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/* for legacy pci hotplug (compatible with qemu 1.6 and older) */
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MemoryRegion io_pci;
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struct pci_status pci0_status;
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uint32_t pci0_hotplug_enable;
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uint32_t pci0_slot_device_present;
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/* for new pci hotplug (with PCI2PCI bridge support) */
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AcpiPciHpState acpi_pci_hotplug;
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bool use_acpi_pci_hotplug;
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@ -170,17 +156,6 @@ static void pm_write_config(PCIDevice *d,
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}
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}
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static void vmstate_pci_status_pre_save(void *opaque)
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{
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struct pci_status *pci0_status = opaque;
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PIIX4PMState *s = container_of(pci0_status, PIIX4PMState, pci0_status);
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/* We no longer track up, so build a safe value for migrating
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* to a version that still does... of course these might get lost
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* by an old buggy implementation, but we try. */
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pci0_status->up = s->pci0_slot_device_present & s->pci0_hotplug_enable;
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}
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static int vmstate_acpi_post_load(void *opaque, int version_id)
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{
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PIIX4PMState *s = opaque;
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@ -216,10 +191,9 @@ static const VMStateDescription vmstate_pci_status = {
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.pre_save = vmstate_pci_status_pre_save,
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.fields = (VMStateField []) {
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VMSTATE_UINT32(up, struct pci_status),
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VMSTATE_UINT32(down, struct pci_status),
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VMSTATE_UINT32(up, struct AcpiPciHpPciStatus),
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VMSTATE_UINT32(down, struct AcpiPciHpPciStatus),
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VMSTATE_END_OF_LIST()
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}
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};
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@ -256,7 +230,8 @@ static int acpi_load_old(QEMUFile *f, void *opaque, int version_id)
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qemu_get_be16s(f, &temp);
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}
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ret = vmstate_load_state(f, &vmstate_pci_status, &s->pci0_status, 1);
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ret = vmstate_load_state(f, &vmstate_pci_status,
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&s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 1);
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return ret;
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}
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@ -294,70 +269,18 @@ static const VMStateDescription vmstate_acpi = {
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VMSTATE_TIMER(ar.tmr.timer, PIIX4PMState),
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VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState),
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VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
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VMSTATE_STRUCT_TEST(pci0_status, PIIX4PMState,
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vmstate_test_no_use_acpi_pci_hotplug,
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2, vmstate_pci_status,
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struct pci_status),
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VMSTATE_STRUCT_TEST(
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acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT],
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PIIX4PMState,
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vmstate_test_no_use_acpi_pci_hotplug,
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2, vmstate_pci_status,
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struct AcpiPciHpPciStatus),
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VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState,
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vmstate_test_use_acpi_pci_hotplug),
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VMSTATE_END_OF_LIST()
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}
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};
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static void acpi_piix_eject_slot(PIIX4PMState *s, unsigned slots)
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{
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BusChild *kid, *next;
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BusState *bus = qdev_get_parent_bus(DEVICE(s));
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int slot = ffs(slots) - 1;
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bool slot_free = true;
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/* Mark request as complete */
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s->pci0_status.down &= ~(1U << slot);
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QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) {
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DeviceState *qdev = kid->child;
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PCIDevice *dev = PCI_DEVICE(qdev);
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PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
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if (PCI_SLOT(dev->devfn) == slot) {
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if (pc->no_hotplug) {
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slot_free = false;
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} else {
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object_unparent(OBJECT(qdev));
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}
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}
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}
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if (slot_free) {
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s->pci0_slot_device_present &= ~(1U << slot);
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}
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}
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static void piix4_update_hotplug(PIIX4PMState *s)
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{
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BusState *bus = qdev_get_parent_bus(DEVICE(s));
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BusChild *kid, *next;
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/* Execute any pending removes during reset */
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while (s->pci0_status.down) {
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acpi_piix_eject_slot(s, s->pci0_status.down);
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}
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s->pci0_hotplug_enable = ~0;
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s->pci0_slot_device_present = 0;
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QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) {
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DeviceState *qdev = kid->child;
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PCIDevice *pdev = PCI_DEVICE(qdev);
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PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pdev);
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int slot = PCI_SLOT(pdev->devfn);
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if (pc->no_hotplug) {
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s->pci0_hotplug_enable &= ~(1U << slot);
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}
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s->pci0_slot_device_present |= (1U << slot);
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}
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}
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static void piix4_reset(void *opaque)
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{
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PIIX4PMState *s = opaque;
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@ -377,11 +300,7 @@ static void piix4_reset(void *opaque)
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pci_conf[0x5B] = 0x02;
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}
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pm_io_space_update(s);
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if (s->use_acpi_pci_hotplug) {
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acpi_pcihp_reset(&s->acpi_pci_hotplug);
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} else {
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piix4_update_hotplug(s);
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}
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acpi_pcihp_reset(&s->acpi_pci_hotplug);
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}
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static void piix4_pm_powerdown_req(Notifier *n, void *opaque)
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@ -428,6 +347,8 @@ static void piix4_pm_machine_ready(Notifier *n, void *opaque)
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if (s->use_acpi_pci_hotplug) {
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pci_for_each_bus(d->bus, piix4_update_bus_hotplug, s);
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} else {
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piix4_update_bus_hotplug(d->bus, s);
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}
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}
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@ -621,60 +542,6 @@ static const MemoryRegionOps piix4_gpe_ops = {
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static uint64_t pci_read(void *opaque, hwaddr addr, unsigned int size)
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{
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PIIX4PMState *s = opaque;
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uint32_t val = 0;
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switch (addr) {
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case PCI_UP_BASE - PCI_HOTPLUG_ADDR:
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/* Manufacture an "up" value to cause a device check on any hotplug
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* slot with a device. Extra device checks are harmless. */
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val = s->pci0_slot_device_present & s->pci0_hotplug_enable;
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PIIX4_DPRINTF("pci_up_read %" PRIu32 "\n", val);
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break;
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case PCI_DOWN_BASE - PCI_HOTPLUG_ADDR:
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val = s->pci0_status.down;
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PIIX4_DPRINTF("pci_down_read %" PRIu32 "\n", val);
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break;
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case PCI_EJ_BASE - PCI_HOTPLUG_ADDR:
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/* No feature defined yet */
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PIIX4_DPRINTF("pci_features_read %" PRIu32 "\n", val);
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break;
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case PCI_RMV_BASE - PCI_HOTPLUG_ADDR:
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val = s->pci0_hotplug_enable;
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break;
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default:
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break;
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}
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return val;
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}
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static void pci_write(void *opaque, hwaddr addr, uint64_t data,
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unsigned int size)
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{
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switch (addr) {
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case PCI_EJ_BASE - PCI_HOTPLUG_ADDR:
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acpi_piix_eject_slot(opaque, (uint32_t)data);
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PIIX4_DPRINTF("pciej write %" HWADDR_PRIx " <== %" PRIu64 "\n",
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addr, data);
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break;
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default:
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break;
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}
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}
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static const MemoryRegionOps piix4_pci_ops = {
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.read = pci_read,
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.write = pci_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static void piix4_cpu_added_req(Notifier *n, void *opaque)
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{
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PIIX4PMState *s = container_of(n, PIIX4PMState, cpu_added_notifier);
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@ -684,9 +551,6 @@ static void piix4_cpu_added_req(Notifier *n, void *opaque)
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acpi_update_sci(&s->ar, s->irq);
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}
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static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
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PCIHotplugState state);
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static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
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PCIBus *bus, PIIX4PMState *s)
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{
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@ -694,56 +558,11 @@ static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
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"acpi-gpe0", GPE_LEN);
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memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe);
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if (s->use_acpi_pci_hotplug) {
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acpi_pcihp_init(&s->acpi_pci_hotplug, bus, parent,
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s->use_acpi_pci_hotplug);
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} else {
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memory_region_init_io(&s->io_pci, OBJECT(s), &piix4_pci_ops, s,
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"acpi-pci-hotplug", PCI_HOTPLUG_SIZE);
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memory_region_add_subregion(parent, PCI_HOTPLUG_ADDR,
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&s->io_pci);
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pci_bus_hotplug(bus, piix4_device_hotplug, DEVICE(s));
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}
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acpi_pcihp_init(&s->acpi_pci_hotplug, bus, parent,
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s->use_acpi_pci_hotplug);
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AcpiCpuHotplug_init(parent, OBJECT(s), &s->gpe_cpu,
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PIIX4_CPU_HOTPLUG_IO_BASE);
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s->cpu_added_notifier.notify = piix4_cpu_added_req;
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qemu_register_cpu_added_notifier(&s->cpu_added_notifier);
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}
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static void enable_device(PIIX4PMState *s, int slot)
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{
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s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS;
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s->pci0_slot_device_present |= (1U << slot);
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}
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static void disable_device(PIIX4PMState *s, int slot)
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{
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s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS;
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s->pci0_status.down |= (1U << slot);
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}
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static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
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PCIHotplugState state)
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{
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int slot = PCI_SLOT(dev->devfn);
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PIIX4PMState *s = PIIX4_PM(qdev);
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/* Don't send event when device is enabled during qemu machine creation:
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* it is present on boot, no hotplug event is necessary. We do send an
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* event when the device is disabled later. */
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if (state == PCI_COLDPLUG_ENABLED) {
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s->pci0_slot_device_present |= (1U << slot);
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return 0;
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}
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if (state == PCI_HOTPLUG_ENABLED) {
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enable_device(s, slot);
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} else {
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disable_device(s, slot);
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}
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acpi_update_sci(&s->ar, s->irq);
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return 0;
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}
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@ -39,6 +39,7 @@ typedef struct AcpiPciHpPciStatus {
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#define ACPI_PCIHP_PROP_BSEL "acpi-pcihp-bsel"
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#define ACPI_PCIHP_MAX_HOTPLUG_BUS 256
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#define ACPI_PCIHP_BSEL_DEFAULT 0x0
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typedef struct AcpiPciHpState {
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AcpiPciHpPciStatus acpi_pcihp_pci_status[ACPI_PCIHP_MAX_HOTPLUG_BUS];
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