target/hppa: Convert remainder of system insns
Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
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c603e14aef
commit
e36f27effb
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@ -23,6 +23,8 @@
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%assemble_sr3 13:1 14:2
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%sm_imm 16:10 !function=expand_sm_imm
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####
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# System
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####
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@ -37,3 +39,13 @@ mtsm 000000 00000 r:5 000 11000011 00000
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mfia 000000 ----- 00000 --- 10100101 t:5
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mfsp 000000 ----- 00000 ... 00100101 t:5 sp=%assemble_sr3
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mfctl 000000 r:5 00000- e:1 -01000101 t:5
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sync 000000 ----- ----- 000 00100000 00000 # sync, syncdma
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ldsid 000000 b:5 ----- sp:2 0 10000101 t:5
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rsm 000000 .......... 000 01110011 t:5 i=%sm_imm
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ssm 000000 .......... 000 01101011 t:5 i=%sm_imm
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rfi 000000 ----- ----- --- 01100000 00000
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rfi_r 000000 ----- ----- --- 01100101 00000
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@ -278,6 +278,18 @@ typedef struct DisasContext {
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bool psw_n_nonzero;
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} DisasContext;
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/* Note that ssm/rsm instructions number PSW_W and PSW_E differently. */
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static int expand_sm_imm(int val)
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{
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if (val & PSW_SM_E) {
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val = (val & ~PSW_SM_E) | PSW_E;
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}
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if (val & PSW_SM_W) {
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val = (val & ~PSW_SM_W) | PSW_W;
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}
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return val;
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}
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/* Include the auto-generated decoder. */
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#include "decode.inc.c"
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@ -1996,7 +2008,7 @@ static bool trans_break(DisasContext *ctx, arg_break *a)
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return gen_excp_iir(ctx, EXCP_BREAK);
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}
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static bool trans_sync(DisasContext *ctx, uint32_t insn, const DisasInsn *di)
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static bool trans_sync(DisasContext *ctx, arg_sync *a)
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{
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/* No point in nullifying the memory barrier. */
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tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL);
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@ -2178,86 +2190,67 @@ static bool trans_mtsarcm(DisasContext *ctx, arg_mtsarcm *a)
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return true;
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}
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static bool trans_ldsid(DisasContext *ctx, uint32_t insn, const DisasInsn *di)
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static bool trans_ldsid(DisasContext *ctx, arg_ldsid *a)
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{
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unsigned rt = extract32(insn, 0, 5);
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TCGv_reg dest = dest_gpr(ctx, rt);
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TCGv_reg dest = dest_gpr(ctx, a->t);
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#ifdef CONFIG_USER_ONLY
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/* We don't implement space registers in user mode. */
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tcg_gen_movi_reg(dest, 0);
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#else
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unsigned rb = extract32(insn, 21, 5);
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unsigned sp = extract32(insn, 14, 2);
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TCGv_i64 t0 = tcg_temp_new_i64();
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tcg_gen_mov_i64(t0, space_select(ctx, sp, load_gpr(ctx, rb)));
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tcg_gen_mov_i64(t0, space_select(ctx, a->sp, load_gpr(ctx, a->b)));
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tcg_gen_shri_i64(t0, t0, 32);
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tcg_gen_trunc_i64_reg(dest, t0);
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tcg_temp_free_i64(t0);
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#endif
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save_gpr(ctx, rt, dest);
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save_gpr(ctx, a->t, dest);
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cond_free(&ctx->null_cond);
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return true;
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}
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static bool trans_rsm(DisasContext *ctx, arg_rsm *a)
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{
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CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
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#ifndef CONFIG_USER_ONLY
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/* Note that ssm/rsm instructions number PSW_W and PSW_E differently. */
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static target_ureg extract_sm_imm(uint32_t insn)
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{
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target_ureg val = extract32(insn, 16, 10);
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if (val & PSW_SM_E) {
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val = (val & ~PSW_SM_E) | PSW_E;
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}
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if (val & PSW_SM_W) {
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val = (val & ~PSW_SM_W) | PSW_W;
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}
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return val;
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}
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static bool trans_rsm(DisasContext *ctx, uint32_t insn, const DisasInsn *di)
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{
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unsigned rt = extract32(insn, 0, 5);
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target_ureg sm = extract_sm_imm(insn);
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TCGv_reg tmp;
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CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
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nullify_over(ctx);
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tmp = get_temp(ctx);
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tcg_gen_ld_reg(tmp, cpu_env, offsetof(CPUHPPAState, psw));
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tcg_gen_andi_reg(tmp, tmp, ~sm);
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tcg_gen_andi_reg(tmp, tmp, ~a->i);
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gen_helper_swap_system_mask(tmp, cpu_env, tmp);
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save_gpr(ctx, rt, tmp);
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save_gpr(ctx, a->t, tmp);
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/* Exit the TB to recognize new interrupts, e.g. PSW_M. */
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ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT;
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return nullify_end(ctx);
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#endif
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}
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static bool trans_ssm(DisasContext *ctx, uint32_t insn, const DisasInsn *di)
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static bool trans_ssm(DisasContext *ctx, arg_ssm *a)
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{
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unsigned rt = extract32(insn, 0, 5);
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target_ureg sm = extract_sm_imm(insn);
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CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
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#ifndef CONFIG_USER_ONLY
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TCGv_reg tmp;
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CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
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nullify_over(ctx);
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tmp = get_temp(ctx);
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tcg_gen_ld_reg(tmp, cpu_env, offsetof(CPUHPPAState, psw));
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tcg_gen_ori_reg(tmp, tmp, sm);
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tcg_gen_ori_reg(tmp, tmp, a->i);
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gen_helper_swap_system_mask(tmp, cpu_env, tmp);
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save_gpr(ctx, rt, tmp);
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save_gpr(ctx, a->t, tmp);
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/* Exit the TB to recognize new interrupts, e.g. PSW_I. */
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ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT;
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return nullify_end(ctx);
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#endif
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}
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#endif /* !CONFIG_USER_ONLY */
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static bool trans_mtsm(DisasContext *ctx, arg_mtsm *a)
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{
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@ -2276,15 +2269,13 @@ static bool trans_mtsm(DisasContext *ctx, arg_mtsm *a)
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#endif
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}
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#ifndef CONFIG_USER_ONLY
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static bool trans_rfi(DisasContext *ctx, uint32_t insn, const DisasInsn *di)
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static bool do_rfi(DisasContext *ctx, bool rfi_r)
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{
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unsigned comp = extract32(insn, 5, 4);
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CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
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#ifndef CONFIG_USER_ONLY
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nullify_over(ctx);
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if (comp == 5) {
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if (rfi_r) {
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gen_helper_rfi_r(cpu_env);
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} else {
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gen_helper_rfi(cpu_env);
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@ -2298,8 +2289,20 @@ static bool trans_rfi(DisasContext *ctx, uint32_t insn, const DisasInsn *di)
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ctx->base.is_jmp = DISAS_NORETURN;
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return nullify_end(ctx);
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#endif
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}
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static bool trans_rfi(DisasContext *ctx, arg_rfi *a)
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{
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return do_rfi(ctx, false);
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}
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static bool trans_rfi_r(DisasContext *ctx, arg_rfi_r *a)
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{
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return do_rfi(ctx, true);
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}
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#ifndef CONFIG_USER_ONLY
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static bool gen_hlt(DisasContext *ctx, int reset)
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{
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CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
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@ -2314,17 +2317,6 @@ static bool gen_hlt(DisasContext *ctx, int reset)
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}
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#endif /* !CONFIG_USER_ONLY */
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static const DisasInsn table_system[] = {
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{ 0x00000400u, 0xffffffffu, trans_sync }, /* sync */
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{ 0x00100400u, 0xffffffffu, trans_sync }, /* syncdma */
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{ 0x000010a0u, 0xfc1f3fe0u, trans_ldsid },
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#ifndef CONFIG_USER_ONLY
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{ 0x00000e60u, 0xfc00ffe0u, trans_rsm },
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{ 0x00000d60u, 0xfc00ffe0u, trans_ssm },
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{ 0x00000c00u, 0xfffffe1fu, trans_rfi },
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#endif
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};
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static bool trans_base_idx_mod(DisasContext *ctx, uint32_t insn,
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const DisasInsn *di)
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{
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@ -4542,9 +4534,6 @@ static void translate_one(DisasContext *ctx, uint32_t insn)
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opc = extract32(insn, 26, 6);
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switch (opc) {
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case 0x00: /* system op */
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translate_table(ctx, insn, table_system);
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return;
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case 0x01:
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translate_table(ctx, insn, table_mem_mgmt);
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return;
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