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s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE * 

In addition to 32/128bit variants, we also have to support the
"Signal-on-QNaN (SQ)" bit.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20210608092337.12221-16-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
This commit is contained in:
David Hildenbrand 2021-06-08 11:23:26 +02:00 committed by Cornelia Huck
parent acb269a4cd
commit e384332cb5
3 changed files with 121 additions and 12 deletions
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12
target/s390x/helper.h
View File

@ -252,12 +252,24 @@ DEF_HELPER_FLAGS_5(gvec_vfa64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfa128, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_4(gvec_wfc64, void, cptr, cptr, env, i32)
DEF_HELPER_4(gvec_wfk64, void, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfce32, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_5(gvec_vfce32_cc, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfce64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_5(gvec_vfce64_cc, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfce128, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_5(gvec_vfce128_cc, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfch32, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_5(gvec_vfch32_cc, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfch64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_5(gvec_vfch64_cc, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfch128, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_5(gvec_vfch128_cc, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfche32, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_5(gvec_vfche32_cc, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfche64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_5(gvec_vfche64_cc, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfche128, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_5(gvec_vfche128_cc, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vcdg64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vcdlg64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vcgd64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)

57
target/s390x/translate_vx.c.inc
View File

@ -2621,26 +2621,65 @@ static DisasJumpType op_vfc(DisasContext *s, DisasOps *o)
const uint8_t m5 = get_field(s, m5);
const uint8_t m6 = get_field(s, m6);
const bool cs = extract32(m6, 0, 1);
gen_helper_gvec_3_ptr *fn;
if (fpf != FPF_LONG || extract32(m5, 0, 3) || extract32(m6, 1, 3)) {
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
}
const bool sq = extract32(m5, 2, 1);
gen_helper_gvec_3_ptr *fn = NULL;
switch (s->fields.op2) {
case 0xe8:
fn = cs ? gen_helper_gvec_vfce64_cc : gen_helper_gvec_vfce64;
switch (fpf) {
case FPF_SHORT:
fn = cs ? gen_helper_gvec_vfce32_cc : gen_helper_gvec_vfce32;
break;
case FPF_LONG:
fn = cs ? gen_helper_gvec_vfce64_cc : gen_helper_gvec_vfce64;
break;
case FPF_EXT:
fn = cs ? gen_helper_gvec_vfce128_cc : gen_helper_gvec_vfce128;
break;
default:
break;
}
break;
case 0xeb:
fn = cs ? gen_helper_gvec_vfch64_cc : gen_helper_gvec_vfch64;
switch (fpf) {
case FPF_SHORT:
fn = cs ? gen_helper_gvec_vfch32_cc : gen_helper_gvec_vfch32;
break;
case FPF_LONG:
fn = cs ? gen_helper_gvec_vfch64_cc : gen_helper_gvec_vfch64;
break;
case FPF_EXT:
fn = cs ? gen_helper_gvec_vfch128_cc : gen_helper_gvec_vfch128;
break;
default:
break;
}
break;
case 0xea:
fn = cs ? gen_helper_gvec_vfche64_cc : gen_helper_gvec_vfche64;
switch (fpf) {
case FPF_SHORT:
fn = cs ? gen_helper_gvec_vfche32_cc : gen_helper_gvec_vfche32;
break;
case FPF_LONG:
fn = cs ? gen_helper_gvec_vfche64_cc : gen_helper_gvec_vfche64;
break;
case FPF_EXT:
fn = cs ? gen_helper_gvec_vfche128_cc : gen_helper_gvec_vfche128;
break;
default:
break;
}
break;
default:
g_assert_not_reached();
}
if (!fn || extract32(m5, 0, 2) || extract32(m6, 1, 3) ||
(!s390_has_feat(S390_FEAT_VECTOR_ENH) && (fpf != FPF_LONG || sq))) {
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
}
gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2), get_field(s, v3),
cpu_env, m5, fn);
if (cs) {

64
target/s390x/vec_fpu_helper.c
View File

@ -340,6 +340,38 @@ void HELPER(gvec_##NAME##BITS)(const void *v1, const void *v2, \
DEF_GVEC_WFC(wfc, false)
DEF_GVEC_WFC(wfk, true)
typedef bool (*vfc32_fn)(float32 a, float32 b, float_status *status);
static int vfc32(S390Vector *v1, const S390Vector *v2, const S390Vector *v3,
CPUS390XState *env, bool s, vfc32_fn fn, uintptr_t retaddr)
{
uint8_t vxc, vec_exc = 0;
S390Vector tmp = {};
int match = 0;
int i;
for (i = 0; i < 4; i++) {
const float32 a = s390_vec_read_float32(v2, i);
const float32 b = s390_vec_read_float32(v3, i);
/* swap the order of the parameters, so we can use existing functions */
if (fn(b, a, &env->fpu_status)) {
match++;
s390_vec_write_element32(&tmp, i, -1u);
}
vxc = check_ieee_exc(env, i, false, &vec_exc);
if (s || vxc) {
break;
}
}
handle_ieee_exc(env, vxc, vec_exc, retaddr);
*v1 = tmp;
if (match) {
return s || match == 4 ? 0 : 1;
}
return 3;
}
typedef bool (*vfc64_fn)(float64 a, float64 b, float_status *status);
static int vfc64(S390Vector *v1, const S390Vector *v2, const S390Vector *v3,
CPUS390XState *env, bool s, vfc64_fn fn, uintptr_t retaddr)
@ -372,12 +404,35 @@ static int vfc64(S390Vector *v1, const S390Vector *v2, const S390Vector *v3,
return 3;
}
typedef bool (*vfc128_fn)(float128 a, float128 b, float_status *status);
static int vfc128(S390Vector *v1, const S390Vector *v2, const S390Vector *v3,
CPUS390XState *env, bool s, vfc128_fn fn, uintptr_t retaddr)
{
const float128 a = s390_vec_read_float128(v2);
const float128 b = s390_vec_read_float128(v3);
uint8_t vxc, vec_exc = 0;
S390Vector tmp = {};
bool match = false;
/* swap the order of the parameters, so we can use existing functions */
if (fn(b, a, &env->fpu_status)) {
match = true;
s390_vec_write_element64(&tmp, 0, -1ull);
s390_vec_write_element64(&tmp, 1, -1ull);
}
vxc = check_ieee_exc(env, 0, false, &vec_exc);
handle_ieee_exc(env, vxc, vec_exc, retaddr);
*v1 = tmp;
return match ? 0 : 3;
}
#define DEF_GVEC_VFC_B(NAME, OP, BITS) \
void HELPER(gvec_##NAME##BITS)(void *v1, const void *v2, const void *v3, \
CPUS390XState *env, uint32_t desc) \
{ \
const bool se = extract32(simd_data(desc), 3, 1); \
vfc##BITS##_fn fn = float##BITS##_##OP##_quiet; \
const bool sq = extract32(simd_data(desc), 2, 1); \
vfc##BITS##_fn fn = sq ? float##BITS##_##OP : float##BITS##_##OP##_quiet; \
\
vfc##BITS(v1, v2, v3, env, se, fn, GETPC()); \
} \
@ -386,13 +441,16 @@ void HELPER(gvec_##NAME##BITS##_cc)(void *v1, const void *v2, const void *v3, \
CPUS390XState *env, uint32_t desc) \
{ \
const bool se = extract32(simd_data(desc), 3, 1); \
vfc##BITS##_fn fn = float##BITS##_##OP##_quiet; \
const bool sq = extract32(simd_data(desc), 2, 1); \
vfc##BITS##_fn fn = sq ? float##BITS##_##OP : float##BITS##_##OP##_quiet; \
\
env->cc_op = vfc##BITS(v1, v2, v3, env, se, fn, GETPC()); \
}
#define DEF_GVEC_VFC(NAME, OP) \
DEF_GVEC_VFC_B(NAME, OP, 64)
DEF_GVEC_VFC_B(NAME, OP, 32) \
DEF_GVEC_VFC_B(NAME, OP, 64) \
DEF_GVEC_VFC_B(NAME, OP, 128) \
DEF_GVEC_VFC(vfce, eq)
DEF_GVEC_VFC(vfch, lt)