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Third RISC-V PR for 6.1 release 

- Fix MISA in the DisasContext
  - Fix GDB CSR XML generation
  - QOMify the SiFive UART
  - Add support for the OpenTitan timer
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Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210624-2' into staging

Third RISC-V PR for 6.1 release

 - Fix MISA in the DisasContext
 - Fix GDB CSR XML generation
 - QOMify the SiFive UART
 - Add support for the OpenTitan timer

# gpg: Signature made Thu 24 Jun 2021 13:00:26 BST
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20210624-2:
  hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer
  hw/timer: Initial commit of Ibex Timer
  hw/char/ibex_uart: Make the register layout private
  hw/char: QOMify sifive_uart
  hw/char: Consistent function names for sifive_uart
  target/riscv: gdbstub: Fix dynamic CSR XML generation
  target/riscv: Use target_ulong for the DisasContext misa

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2021-06-25 17:05:22 +01:00
parent 3593b8e0a2 3ef6434409
commit e3955ae93f
12 changed files with 543 additions and 81 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
MAINTAINERS
View File

@ -1365,11 +1365,9 @@ M: Alistair Francis <Alistair.Francis@wdc.com>
L: qemu-riscv@nongnu.org
S: Supported
F: hw/riscv/opentitan.c
F: hw/char/ibex_uart.c
F: hw/intc/ibex_plic.c
F: hw/*/ibex_*.c
F: include/hw/riscv/opentitan.h
F: include/hw/char/ibex_uart.h
F: include/hw/intc/ibex_plic.h
F: include/hw/*/ibex_*.h
Microchip PolarFire SoC Icicle Kit
M: Bin Meng <bin.meng@windriver.com>

37
hw/char/ibex_uart.c
View File

@ -35,6 +35,43 @@
#include "qemu/log.h"
#include "qemu/module.h"
REG32(INTR_STATE, 0x00)
FIELD(INTR_STATE, TX_WATERMARK, 0, 1)
FIELD(INTR_STATE, RX_WATERMARK, 1, 1)
FIELD(INTR_STATE, TX_EMPTY, 2, 1)
FIELD(INTR_STATE, RX_OVERFLOW, 3, 1)
REG32(INTR_ENABLE, 0x04)
REG32(INTR_TEST, 0x08)
REG32(CTRL, 0x0C)
FIELD(CTRL, TX_ENABLE, 0, 1)
FIELD(CTRL, RX_ENABLE, 1, 1)
FIELD(CTRL, NF, 2, 1)
FIELD(CTRL, SLPBK, 4, 1)
FIELD(CTRL, LLPBK, 5, 1)
FIELD(CTRL, PARITY_EN, 6, 1)
FIELD(CTRL, PARITY_ODD, 7, 1)
FIELD(CTRL, RXBLVL, 8, 2)
FIELD(CTRL, NCO, 16, 16)
REG32(STATUS, 0x10)
FIELD(STATUS, TXFULL, 0, 1)
FIELD(STATUS, RXFULL, 1, 1)
FIELD(STATUS, TXEMPTY, 2, 1)
FIELD(STATUS, RXIDLE, 4, 1)
FIELD(STATUS, RXEMPTY, 5, 1)
REG32(RDATA, 0x14)
REG32(WDATA, 0x18)
REG32(FIFO_CTRL, 0x1c)
FIELD(FIFO_CTRL, RXRST, 0, 1)
FIELD(FIFO_CTRL, TXRST, 1, 1)
FIELD(FIFO_CTRL, RXILVL, 2, 3)
FIELD(FIFO_CTRL, TXILVL, 5, 2)
REG32(FIFO_STATUS, 0x20)
FIELD(FIFO_STATUS, TXLVL, 0, 5)
FIELD(FIFO_STATUS, RXLVL, 16, 5)
REG32(OVRD, 0x24)
REG32(VAL, 0x28)
REG32(TIMEOUT_CTRL, 0x2c)
static void ibex_uart_update_irqs(IbexUartState *s)
{
if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_TX_WATERMARK_MASK) {

152
hw/char/sifive_uart.c
View File

@ -19,10 +19,12 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu/log.h"
#include "migration/vmstate.h"
#include "chardev/char.h"
#include "chardev/char-fe.h"
#include "hw/irq.h"
#include "hw/char/sifive_uart.h"
#include "hw/qdev-properties-system.h"
/*
* Not yet implemented:
@ -31,7 +33,7 @@
*/
/* Returns the state of the IP (interrupt pending) register */
static uint64_t uart_ip(SiFiveUARTState *s)
static uint64_t sifive_uart_ip(SiFiveUARTState *s)
{
uint64_t ret = 0;
@ -48,7 +50,7 @@ static uint64_t uart_ip(SiFiveUARTState *s)
return ret;
}
static void update_irq(SiFiveUARTState *s)
static void sifive_uart_update_irq(SiFiveUARTState *s)
{
int cond = 0;
if ((s->ie & SIFIVE_UART_IE_TXWM) ||
@ -63,7 +65,7 @@ static void update_irq(SiFiveUARTState *s)
}
static uint64_t
uart_read(void *opaque, hwaddr addr, unsigned int size)
sifive_uart_read(void *opaque, hwaddr addr, unsigned int size)
{
SiFiveUARTState *s = opaque;
unsigned char r;
@ -74,7 +76,7 @@ uart_read(void *opaque, hwaddr addr, unsigned int size)
memmove(s->rx_fifo, s->rx_fifo + 1, s->rx_fifo_len - 1);
s->rx_fifo_len--;
qemu_chr_fe_accept_input(&s->chr);
update_irq(s);
sifive_uart_update_irq(s);
return r;
}
return 0x80000000;
@ -84,7 +86,7 @@ uart_read(void *opaque, hwaddr addr, unsigned int size)
case SIFIVE_UART_IE:
return s->ie;
case SIFIVE_UART_IP:
return uart_ip(s);
return sifive_uart_ip(s);
case SIFIVE_UART_TXCTRL:
return s->txctrl;
case SIFIVE_UART_RXCTRL:
@ -99,8 +101,8 @@ uart_read(void *opaque, hwaddr addr, unsigned int size)
}
static void
uart_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
sifive_uart_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
SiFiveUARTState *s = opaque;
uint32_t value = val64;
@ -109,11 +111,11 @@ uart_write(void *opaque, hwaddr addr,
switch (addr) {
case SIFIVE_UART_TXFIFO:
qemu_chr_fe_write(&s->chr, &ch, 1);
update_irq(s);
sifive_uart_update_irq(s);
return;
case SIFIVE_UART_IE:
s->ie = val64;
update_irq(s);
sifive_uart_update_irq(s);
return;
case SIFIVE_UART_TXCTRL:
s->txctrl = val64;
@ -129,9 +131,9 @@ uart_write(void *opaque, hwaddr addr,
__func__, (int)addr, (int)value);
}
static const MemoryRegionOps uart_ops = {
.read = uart_read,
.write = uart_write,
static const MemoryRegionOps sifive_uart_ops = {
.read = sifive_uart_read,
.write = sifive_uart_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 4,
@ -139,7 +141,7 @@ static const MemoryRegionOps uart_ops = {
}
};
static void uart_rx(void *opaque, const uint8_t *buf, int size)
static void sifive_uart_rx(void *opaque, const uint8_t *buf, int size)
{
SiFiveUARTState *s = opaque;
@ -150,43 +152,137 @@ static void uart_rx(void *opaque, const uint8_t *buf, int size)
}
s->rx_fifo[s->rx_fifo_len++] = *buf;
update_irq(s);
sifive_uart_update_irq(s);
}
static int uart_can_rx(void *opaque)
static int sifive_uart_can_rx(void *opaque)
{
SiFiveUARTState *s = opaque;
return s->rx_fifo_len < sizeof(s->rx_fifo);
}
static void uart_event(void *opaque, QEMUChrEvent event)
static void sifive_uart_event(void *opaque, QEMUChrEvent event)
{
}
static int uart_be_change(void *opaque)
static int sifive_uart_be_change(void *opaque)
{
SiFiveUARTState *s = opaque;
qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event,
uart_be_change, s, NULL, true);
qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx,
sifive_uart_event, sifive_uart_be_change, s,
NULL, true);
return 0;
}
static Property sifive_uart_properties[] = {
DEFINE_PROP_CHR("chardev", SiFiveUARTState, chr),
DEFINE_PROP_END_OF_LIST(),
};
static void sifive_uart_init(Object *obj)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
SiFiveUARTState *s = SIFIVE_UART(obj);
memory_region_init_io(&s->mmio, OBJECT(s), &sifive_uart_ops, s,
TYPE_SIFIVE_UART, SIFIVE_UART_MAX);
sysbus_init_mmio(sbd, &s->mmio);
sysbus_init_irq(sbd, &s->irq);
}
static void sifive_uart_realize(DeviceState *dev, Error **errp)
{
SiFiveUARTState *s = SIFIVE_UART(dev);
qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx,
sifive_uart_event, sifive_uart_be_change, s,
NULL, true);
}
static void sifive_uart_reset_enter(Object *obj, ResetType type)
{
SiFiveUARTState *s = SIFIVE_UART(obj);
s->ie = 0;
s->ip = 0;
s->txctrl = 0;
s->rxctrl = 0;
s->div = 0;
s->rx_fifo_len = 0;
}
static void sifive_uart_reset_hold(Object *obj)
{
SiFiveUARTState *s = SIFIVE_UART(obj);
qemu_irq_lower(s->irq);
}
static const VMStateDescription vmstate_sifive_uart = {
.name = TYPE_SIFIVE_UART,
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT8_ARRAY(rx_fifo, SiFiveUARTState,
SIFIVE_UART_RX_FIFO_SIZE),
VMSTATE_UINT8(rx_fifo_len, SiFiveUARTState),
VMSTATE_UINT32(ie, SiFiveUARTState),
VMSTATE_UINT32(ip, SiFiveUARTState),
VMSTATE_UINT32(txctrl, SiFiveUARTState),
VMSTATE_UINT32(rxctrl, SiFiveUARTState),
VMSTATE_UINT32(div, SiFiveUARTState),
VMSTATE_END_OF_LIST()
},
};
static void sifive_uart_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
ResettableClass *rc = RESETTABLE_CLASS(oc);
dc->realize = sifive_uart_realize;
dc->vmsd = &vmstate_sifive_uart;
rc->phases.enter = sifive_uart_reset_enter;
rc->phases.hold = sifive_uart_reset_hold;
device_class_set_props(dc, sifive_uart_properties);
}
static const TypeInfo sifive_uart_info = {
.name = TYPE_SIFIVE_UART,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(SiFiveUARTState),
.instance_init = sifive_uart_init,
.class_init = sifive_uart_class_init,
};
static void sifive_uart_register_types(void)
{
type_register_static(&sifive_uart_info);
}
type_init(sifive_uart_register_types)
/*
* Create UART device.
*/
SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base,
Chardev *chr, qemu_irq irq)
{
SiFiveUARTState *s = g_malloc0(sizeof(SiFiveUARTState));
s->irq = irq;
qemu_chr_fe_init(&s->chr, chr, &error_abort);
qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event,
uart_be_change, s, NULL, true);
memory_region_init_io(&s->mmio, NULL, &uart_ops, s,
TYPE_SIFIVE_UART, SIFIVE_UART_MAX);
memory_region_add_subregion(address_space, base, &s->mmio);
return s;
DeviceState *dev;
SysBusDevice *s;
SiFiveUARTState *r;
dev = qdev_new("riscv.sifive.uart");
s = SYS_BUS_DEVICE(dev);
qdev_prop_set_chr(dev, "chardev", chr);
sysbus_realize_and_unref(s, &error_fatal);
memory_region_add_subregion(address_space, base,
sysbus_mmio_get_region(s, 0));
sysbus_connect_irq(s, 0, irq);
r = SIFIVE_UART(dev);
return r;
}

14
hw/riscv/opentitan.c
View File

@ -36,7 +36,7 @@ static const MemMapEntry ibex_memmap[] = {
[IBEX_DEV_SPI] = { 0x40050000, 0x1000 },
[IBEX_DEV_I2C] = { 0x40080000, 0x1000 },
[IBEX_DEV_PATTGEN] = { 0x400e0000, 0x1000 },
[IBEX_DEV_RV_TIMER] = { 0x40100000, 0x1000 },
[IBEX_DEV_TIMER] = { 0x40100000, 0x1000 },
[IBEX_DEV_SENSOR_CTRL] = { 0x40110000, 0x1000 },
[IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x4000 },
[IBEX_DEV_PWRMGR] = { 0x40400000, 0x1000 },
@ -106,6 +106,8 @@ static void lowrisc_ibex_soc_init(Object *obj)
object_initialize_child(obj, "plic", &s->plic, TYPE_IBEX_PLIC);
object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART);
object_initialize_child(obj, "timer", &s->timer, TYPE_IBEX_TIMER);
}
static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
@ -159,6 +161,14 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
3, qdev_get_gpio_in(DEVICE(&s->plic),
IBEX_UART0_RX_OVERFLOW_IRQ));
if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) {
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, memmap[IBEX_DEV_TIMER].base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer),
0, qdev_get_gpio_in(DEVICE(&s->plic),
IBEX_TIMER_TIMEREXPIRED0_0));
create_unimplemented_device("riscv.lowrisc.ibex.gpio",
memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
create_unimplemented_device("riscv.lowrisc.ibex.spi",
@ -167,8 +177,6 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size);
create_unimplemented_device("riscv.lowrisc.ibex.pattgen",
memmap[IBEX_DEV_PATTGEN].base, memmap[IBEX_DEV_PATTGEN].size);
create_unimplemented_device("riscv.lowrisc.ibex.rv_timer",
memmap[IBEX_DEV_RV_TIMER].base, memmap[IBEX_DEV_RV_TIMER].size);
create_unimplemented_device("riscv.lowrisc.ibex.sensor_ctrl",
memmap[IBEX_DEV_SENSOR_CTRL].base, memmap[IBEX_DEV_SENSOR_CTRL].size);
create_unimplemented_device("riscv.lowrisc.ibex.otp_ctrl",

305
hw/timer/ibex_timer.c Normal file
View File

@ -0,0 +1,305 @@
/*
* QEMU lowRISC Ibex Timer device
*
* Copyright (c) 2021 Western Digital
*
* For details check the documentation here:
* https://docs.opentitan.org/hw/ip/rv_timer/doc/
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "qemu/timer.h"
#include "hw/timer/ibex_timer.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "target/riscv/cpu.h"
#include "migration/vmstate.h"
REG32(CTRL, 0x00)
FIELD(CTRL, ACTIVE, 0, 1)
REG32(CFG0, 0x100)
FIELD(CFG0, PRESCALE, 0, 12)
FIELD(CFG0, STEP, 16, 8)
REG32(LOWER0, 0x104)
REG32(UPPER0, 0x108)
REG32(COMPARE_LOWER0, 0x10C)
REG32(COMPARE_UPPER0, 0x110)
REG32(INTR_ENABLE, 0x114)
FIELD(INTR_ENABLE, IE_0, 0, 1)
REG32(INTR_STATE, 0x118)
FIELD(INTR_STATE, IS_0, 0, 1)
REG32(INTR_TEST, 0x11C)
FIELD(INTR_TEST, T_0, 0, 1)
static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)
{
return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
timebase_freq, NANOSECONDS_PER_SECOND);
}
static void ibex_timer_update_irqs(IbexTimerState *s)
{
CPUState *cs = qemu_get_cpu(0);
RISCVCPU *cpu = RISCV_CPU(cs);
uint64_t value = s->timer_compare_lower0 |
((uint64_t)s->timer_compare_upper0 << 32);
uint64_t next, diff;
uint64_t now = cpu_riscv_read_rtc(s->timebase_freq);
if (!(s->timer_ctrl & R_CTRL_ACTIVE_MASK)) {
/* Timer isn't active */
return;
}
/* Update the CPUs mtimecmp */
cpu->env.timecmp = value;
if (cpu->env.timecmp <= now) {
/*
* If the mtimecmp was in the past raise the interrupt now.
*/
riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(1));
if (s->timer_intr_enable & R_INTR_ENABLE_IE_0_MASK) {
s->timer_intr_state |= R_INTR_STATE_IS_0_MASK;
qemu_set_irq(s->irq, true);
}
return;
}
/* Setup a timer to trigger the interrupt in the future */
riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(0));
qemu_set_irq(s->irq, false);
diff = cpu->env.timecmp - now;
next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
muldiv64(diff,
NANOSECONDS_PER_SECOND,
s->timebase_freq);
if (next < qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) {
/* We overflowed the timer, just set it as large as we can */
timer_mod(cpu->env.timer, 0x7FFFFFFFFFFFFFFF);
} else {
timer_mod(cpu->env.timer, next);
}
}
static void ibex_timer_cb(void *opaque)
{
IbexTimerState *s = opaque;
CPUState *cs = qemu_get_cpu(0);
RISCVCPU *cpu = RISCV_CPU(cs);
riscv_cpu_update_mip(cpu, MIP_MTIP, BOOL_TO_MASK(1));
if (s->timer_intr_enable & R_INTR_ENABLE_IE_0_MASK) {
s->timer_intr_state |= R_INTR_STATE_IS_0_MASK;
qemu_set_irq(s->irq, true);
}
}
static void ibex_timer_reset(DeviceState *dev)
{
IbexTimerState *s = IBEX_TIMER(dev);
CPUState *cpu = qemu_get_cpu(0);
CPURISCVState *env = cpu->env_ptr;
env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
&ibex_timer_cb, s);
env->timecmp = 0;
s->timer_ctrl = 0x00000000;
s->timer_cfg0 = 0x00010000;
s->timer_compare_lower0 = 0xFFFFFFFF;
s->timer_compare_upper0 = 0xFFFFFFFF;
s->timer_intr_enable = 0x00000000;
s->timer_intr_state = 0x00000000;
s->timer_intr_test = 0x00000000;
ibex_timer_update_irqs(s);
}
static uint64_t ibex_timer_read(void *opaque, hwaddr addr,
unsigned int size)
{
IbexTimerState *s = opaque;
uint64_t now = cpu_riscv_read_rtc(s->timebase_freq);
uint64_t retvalue = 0;
switch (addr >> 2) {
case R_CTRL:
retvalue = s->timer_ctrl;
break;
case R_CFG0:
retvalue = s->timer_cfg0;
break;
case R_LOWER0:
retvalue = now;
break;
case R_UPPER0:
retvalue = now >> 32;
break;
case R_COMPARE_LOWER0:
retvalue = s->timer_compare_lower0;
break;
case R_COMPARE_UPPER0:
retvalue = s->timer_compare_upper0;
break;
case R_INTR_ENABLE:
retvalue = s->timer_intr_enable;
break;
case R_INTR_STATE:
retvalue = s->timer_intr_state;
break;
case R_INTR_TEST:
retvalue = s->timer_intr_test;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
return 0;
}
return retvalue;
}
static void ibex_timer_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
IbexTimerState *s = opaque;
uint32_t val = val64;
switch (addr >> 2) {
case R_CTRL:
s->timer_ctrl = val;
break;
case R_CFG0:
qemu_log_mask(LOG_UNIMP, "Changing prescale or step not supported");
s->timer_cfg0 = val;
break;
case R_LOWER0:
qemu_log_mask(LOG_UNIMP, "Changing timer value is not supported");
break;
case R_UPPER0:
qemu_log_mask(LOG_UNIMP, "Changing timer value is not supported");
break;
case R_COMPARE_LOWER0:
s->timer_compare_lower0 = val;
ibex_timer_update_irqs(s);
break;
case R_COMPARE_UPPER0:
s->timer_compare_upper0 = val;
ibex_timer_update_irqs(s);
break;
case R_INTR_ENABLE:
s->timer_intr_enable = val;
break;
case R_INTR_STATE:
/* Write 1 to clear */
s->timer_intr_state &= ~val;
break;
case R_INTR_TEST:
s->timer_intr_test = val;
if (s->timer_intr_enable &
s->timer_intr_test &
R_INTR_ENABLE_IE_0_MASK) {
s->timer_intr_state |= R_INTR_STATE_IS_0_MASK;
qemu_set_irq(s->irq, true);
}
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
}
}
static const MemoryRegionOps ibex_timer_ops = {
.read = ibex_timer_read,
.write = ibex_timer_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.impl.min_access_size = 4,
.impl.max_access_size = 4,
};
static int ibex_timer_post_load(void *opaque, int version_id)
{
IbexTimerState *s = opaque;
ibex_timer_update_irqs(s);
return 0;
}
static const VMStateDescription vmstate_ibex_timer = {
.name = TYPE_IBEX_TIMER,
.version_id = 1,
.minimum_version_id = 1,
.post_load = ibex_timer_post_load,
.fields = (VMStateField[]) {
VMSTATE_UINT32(timer_ctrl, IbexTimerState),
VMSTATE_UINT32(timer_cfg0, IbexTimerState),
VMSTATE_UINT32(timer_compare_lower0, IbexTimerState),
VMSTATE_UINT32(timer_compare_upper0, IbexTimerState),
VMSTATE_UINT32(timer_intr_enable, IbexTimerState),
VMSTATE_UINT32(timer_intr_state, IbexTimerState),
VMSTATE_UINT32(timer_intr_test, IbexTimerState),
VMSTATE_END_OF_LIST()
}
};
static Property ibex_timer_properties[] = {
DEFINE_PROP_UINT32("timebase-freq", IbexTimerState, timebase_freq, 10000),
DEFINE_PROP_END_OF_LIST(),
};
static void ibex_timer_init(Object *obj)
{
IbexTimerState *s = IBEX_TIMER(obj);
sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
memory_region_init_io(&s->mmio, obj, &ibex_timer_ops, s,
TYPE_IBEX_TIMER, 0x400);
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
}
static void ibex_timer_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = ibex_timer_reset;
dc->vmsd = &vmstate_ibex_timer;
device_class_set_props(dc, ibex_timer_properties);
}
static const TypeInfo ibex_timer_info = {
.name = TYPE_IBEX_TIMER,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(IbexTimerState),
.instance_init = ibex_timer_init,
.class_init = ibex_timer_class_init,
};
static void ibex_timer_register_types(void)
{
type_register_static(&ibex_timer_info);
}
type_init(ibex_timer_register_types)

1
hw/timer/meson.build
View File

@ -33,5 +33,6 @@ softmmu_ss.add(when: 'CONFIG_SSE_COUNTER', if_true: files('sse-counter.c'))
softmmu_ss.add(when: 'CONFIG_SSE_TIMER', if_true: files('sse-timer.c'))
softmmu_ss.add(when: 'CONFIG_STM32F2XX_TIMER', if_true: files('stm32f2xx_timer.c'))
softmmu_ss.add(when: 'CONFIG_XILINX', if_true: files('xilinx_timer.c'))
specific_ss.add(when: 'CONFIG_IBEX', if_true: files('ibex_timer.c'))
specific_ss.add(when: 'CONFIG_AVR_TIMER16', if_true: files('avr_timer16.c'))

37
include/hw/char/ibex_uart.h
View File

@ -31,43 +31,6 @@
#include "qemu/timer.h"
#include "qom/object.h"
REG32(INTR_STATE, 0x00)
FIELD(INTR_STATE, TX_WATERMARK, 0, 1)
FIELD(INTR_STATE, RX_WATERMARK, 1, 1)
FIELD(INTR_STATE, TX_EMPTY, 2, 1)
FIELD(INTR_STATE, RX_OVERFLOW, 3, 1)
REG32(INTR_ENABLE, 0x04)
REG32(INTR_TEST, 0x08)
REG32(CTRL, 0x0C)
FIELD(CTRL, TX_ENABLE, 0, 1)
FIELD(CTRL, RX_ENABLE, 1, 1)
FIELD(CTRL, NF, 2, 1)
FIELD(CTRL, SLPBK, 4, 1)
FIELD(CTRL, LLPBK, 5, 1)
FIELD(CTRL, PARITY_EN, 6, 1)
FIELD(CTRL, PARITY_ODD, 7, 1)
FIELD(CTRL, RXBLVL, 8, 2)
FIELD(CTRL, NCO, 16, 16)
REG32(STATUS, 0x10)
FIELD(STATUS, TXFULL, 0, 1)
FIELD(STATUS, RXFULL, 1, 1)
FIELD(STATUS, TXEMPTY, 2, 1)
FIELD(STATUS, RXIDLE, 4, 1)
FIELD(STATUS, RXEMPTY, 5, 1)
REG32(RDATA, 0x14)
REG32(WDATA, 0x18)
REG32(FIFO_CTRL, 0x1c)
FIELD(FIFO_CTRL, RXRST, 0, 1)
FIELD(FIFO_CTRL, TXRST, 1, 1)
FIELD(FIFO_CTRL, RXILVL, 2, 3)
FIELD(FIFO_CTRL, TXILVL, 5, 2)
REG32(FIFO_STATUS, 0x20)
FIELD(FIFO_STATUS, TXLVL, 0, 5)
FIELD(FIFO_STATUS, RXLVL, 16, 5)
REG32(OVRD, 0x24)
REG32(VAL, 0x28)
REG32(TIMEOUT_CTRL, 0x2c)
#define IBEX_UART_TX_FIFO_SIZE 16
#define IBEX_UART_CLOCK 50000000 /* 50MHz clock */

11
include/hw/char/sifive_uart.h
View File

@ -21,6 +21,7 @@
#define HW_SIFIVE_UART_H
#include "chardev/char-fe.h"
#include "hw/qdev-properties.h"
#include "hw/sysbus.h"
#include "qom/object.h"
@ -49,12 +50,10 @@ enum {
#define SIFIVE_UART_GET_TXCNT(txctrl) ((txctrl >> 16) & 0x7)
#define SIFIVE_UART_GET_RXCNT(rxctrl) ((rxctrl >> 16) & 0x7)
#define SIFIVE_UART_RX_FIFO_SIZE 8
#define TYPE_SIFIVE_UART "riscv.sifive.uart"
typedef struct SiFiveUARTState SiFiveUARTState;
DECLARE_INSTANCE_CHECKER(SiFiveUARTState, SIFIVE_UART,
TYPE_SIFIVE_UART)
OBJECT_DECLARE_SIMPLE_TYPE(SiFiveUARTState, SIFIVE_UART)
struct SiFiveUARTState {
/*< private >*/
@ -64,8 +63,8 @@ struct SiFiveUARTState {
qemu_irq irq;
MemoryRegion mmio;
CharBackend chr;
uint8_t rx_fifo[8];
unsigned int rx_fifo_len;
uint8_t rx_fifo[SIFIVE_UART_RX_FIFO_SIZE];
uint8_t rx_fifo_len;
uint32_t ie;
uint32_t ip;
uint32_t txctrl;

5
include/hw/riscv/opentitan.h
View File

@ -22,6 +22,7 @@
#include "hw/riscv/riscv_hart.h"
#include "hw/intc/ibex_plic.h"
#include "hw/char/ibex_uart.h"
#include "hw/timer/ibex_timer.h"
#include "qom/object.h"
#define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc"
@ -35,6 +36,7 @@ struct LowRISCIbexSoCState {
RISCVHartArrayState cpus;
IbexPlicState plic;
IbexUartState uart;
IbexTimerState timer;
MemoryRegion flash_mem;
MemoryRegion rom;
@ -57,7 +59,7 @@ enum {
IBEX_DEV_SPI,
IBEX_DEV_I2C,
IBEX_DEV_PATTGEN,
IBEX_DEV_RV_TIMER,
IBEX_DEV_TIMER,
IBEX_DEV_SENSOR_CTRL,
IBEX_DEV_OTP_CTRL,
IBEX_DEV_PWRMGR,
@ -82,6 +84,7 @@ enum {
};
enum {
IBEX_TIMER_TIMEREXPIRED0_0 = 125,
IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
IBEX_UART0_RX_TIMEOUT_IRQ = 7,
IBEX_UART0_RX_BREAK_ERR_IRQ = 6,

52
include/hw/timer/ibex_timer.h Normal file
View File

@ -0,0 +1,52 @@
/*
* QEMU lowRISC Ibex Timer device
*
* Copyright (c) 2021 Western Digital
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef HW_IBEX_TIMER_H
#define HW_IBEX_TIMER_H
#include "hw/sysbus.h"
#define TYPE_IBEX_TIMER "ibex-timer"
OBJECT_DECLARE_SIMPLE_TYPE(IbexTimerState, IBEX_TIMER)
struct IbexTimerState {
/* <private> */
SysBusDevice parent_obj;
/* <public> */
MemoryRegion mmio;
uint32_t timer_ctrl;
uint32_t timer_cfg0;
uint32_t timer_compare_lower0;
uint32_t timer_compare_upper0;
uint32_t timer_intr_enable;
uint32_t timer_intr_state;
uint32_t timer_intr_test;
uint32_t timebase_freq;
qemu_irq irq;
};
#endif /* HW_IBEX_TIMER_H */

2
target/riscv/gdbstub.c
View File

@ -170,7 +170,7 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg)
for (i = 0; i < CSR_TABLE_SIZE; i++) {
predicate = csr_ops[i].predicate;
if (predicate && !predicate(env, i)) {
if (predicate && (predicate(env, i) == RISCV_EXCP_NONE)) {
if (csr_ops[i].name) {
g_string_append_printf(s, "<reg name=\"%s\"", csr_ops[i].name);
} else {

2
target/riscv/translate.c
View File

@ -47,7 +47,7 @@ typedef struct DisasContext {
bool virt_enabled;
uint32_t opcode;
uint32_t mstatus_fs;
uint32_t misa;
target_ulong misa;
uint32_t mem_idx;
/* Remember the rounding mode encoded in the previous fp instruction,
which we have already installed into env->fp_status. Or -1 for